FPGA可编程逻辑器件芯片XQ4036XL-4PG411M中文规格书 - 图文

Configuration Interfaces

Virtex?-5 devices have six configuration interfaces. Each configuration interface

corresponds to one or more configuration modes and bus width, shown in Table2-1. For detailed interface timing information, see DS202, Virtex-5 FPGA Data Sheet: DC and Switching Characteristic.

Table 2-1:Virtex-5 Device Configuration Modes

Configuration ModeMaster Serial(2)Master SPI(2)Master BPI-Up(2)Master BPI-Down(2)Master SelectMAP(2)JTAG

Slave SelectMAPSlave Serial

Notes:

1.Parallel configuration mode bus is auto-detected by the configuration logic.

2.In Master configuration mode, the CCLK pin is the clock source for the Virtex-5 internal configuration logic. The Virtex-5 CCLK output pin must be free from reflections to avoid double-clocking the

internal configuration logic. Refer to the “Board Layout for Configuration Clock (CCLK)” section formore details.

M[2:0]000001010011100101110111

Bus Width

118, 168, 168, 1618, 16, 32

1

CCLK Direction

OutputOutputOutputOutputOutputInput (TCK)InputInput

Serial Configuration Interface

In serial configuration modes, the FPGA is configured by loading one configuration bit per CCLK cycle:??

In Master Serial mode, CCLK is an output.In Slave Serial mode, CCLK is an input.

Figure2-1 shows the basic Virtex-5 serial configuration interface.There are four methods of configuring an FPGA in serial mode:???

Master serial configurationSlave serial configurationSerial daisy-chain configuration

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020

Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1

TAP Controller

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020

Chapter 3:Boundary-Scan and JTAG Configuration

Capture-DR:

In this controller state, the data is parallel-loaded into the data registers selected by the current instruction on the rising edge of TCK.

Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR:

These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, and Update-IR states in the Instruction path.

10TEST-LOGIC-RESET0RUN-TEST/IDLE1SELECT-DR-SCAN10CAPTURE-DR0SHIFT-DR1EXIT1-DR0PAUSE-DR01EXIT2-DR1UPDATE-DR10100101SELECT-IR-SCAN10CAPTURE-IR0SHIFT-IR1EXIT1-IR0PAUSE-IR1EXIT2-IR1UPDATE-IR00101NOTE: The value shown adjacent to each state transition in this figurerepresents the signal present at TMS at the time of a rising edge at TCK.

UG191_c3_02_050406

Figure 3-2:Boundary-Scan TAP Controller

Virtex-5 devices support the mandatory IEEE 1149.1 commands, as well as several Xilinx vendor-specific commands. The EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,

IDCODE, USERCODE, and HIGHZ instructions are all included. The TAP also supports internal user-defined registers (USER1, USER2, USER3, and USER4) and configuration/readback of the device.

The Virtex-5 Boundary-Scan operations are independent of mode selection. The

Boundary-Scan mode in Virtex-5 devices overrides other mode selections. For this reason, Boundary-Scan instructions using the Boundary-Scan register (SAMPLE/PRELOAD, INTEST, and EXTEST) must not be performed during configuration. All instructions except the user-defined instructions are available before a Virtex-5 device is configured. After configuration, all instructions are available.

JSTART and JSHUTDOWN are instructions specific to the Virtex-5 architecture and

configuration flow. In Virtex-5 devices, the TAP controller is not reset by the PROGRAM_B pin and can only be reset by bringing the controller to the TLR state. The TAP controller is reset on power up.

For details on the standard Boundary-Scan instructions EXTEST, INTEST, and BYPASS, refer to the IEEE Standard.

Virtex-5 FPGA Configuration Guide

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Chapter 3:Boundary-Scan and JTAG Configuration

TDI?Notes:

IR[9:6]Reserved

IR[5]DONE

IR[4]INIT(1)

IR[3]ISC_ENABLED

IR[2]ISC_DONE

IR[1:0]0 1

?TDO

1.INIT is the status bit of the INIT_COMPLETE signal.

Figure 3-4:

Virtex-5 Device Instruction Capture Values Loaded into IR as Part of an Instruction Scan

Sequence

BYPASS Register

The other standard data register is the single flip-flop BYPASS register. It passes data serially from the TDI pin to the TDO pin during a bypass instruction. This register is initialized to zero when the TAP controller is in the CAPTURE-DR state.

Identification (IDCODE) Register

Virtex devices have a 32-bit identification register called the IDCODE register. The

IDCODE is based on the IEEE 1149.1 standard, and is a fixed, vendor-assigned value that is used to identify electrically the manufacturer and the type of device that is being

addressed. This register allows easy identification of the part being tested or programmed by Boundary-Scan, and it can be shifted out for examination by using the IDCODE instruction.

The last bit of the IDCODE is always 1 (based on JTAG IEEE 1149.1). The last three hex digits appear as 0x093. IDCODEs assigned to Virtex-5 FPGAs are shown in Table1-13, page29.

JTAG Configuration Register

The JTAG Configuration register is a 32-bit register. This register allows access to the configuration bus and readback operations.

USERCODE Register

The USERCODE instruction is supported in the Virtex-5 family. This register allows a user to specify a design-specific identification code. The USERCODE can be programmed into the device and can be read back for verification later. The USERCODE is embedded into the bitstream during bitstream generation (BitGen -g UserID option) and is valid only after configuration. If the device is blank or the USERCODE was not programmed, the USERCODE register contains 0xFFFFFFFF.

USER1, USER2, USER3, and USER4 Registers

The USER1, USER2, USER3, and USER4 registers are only available after configuration. These four registers must be defined by the user within the design. These registers can be accessed after they are defined by the TAP pins.

The BSCAN_VIRTEX5 library macro is required when creating these registers. This symbol is only required for driving internal scan chains (USER1, USER2, USER3, and USER4). A common input pin (TDI) and shared output pins represent the state of the TAP controller (RESET, SHIFT, and UPDATE). Virtex-5 TAP pins are dedicated and do not require the BSCAN_VIRTEX5 macro for normal Boundary-Scan instructions or operations. For HDL, the BSCAN_VIRTEX5 macro must be instantiated in the design.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1

Using Boundary-Scan in Virtex-5 Devices

Characterization data for some of the most commonly requested timing parameters shown in Figure3-5 are listed in DS202, Virtex-5 Data Sheet: DC and Switching Characteristics, in the Configuration Switching Characteristics table.

TMSTDI

TTAPTCKTTCKTAPTCK

TTCKTDOTDO

Data to be capturedData to be driven out

Data ValidData Valid

UG191_c3_05_050406

Figure 3-5:Virtex-5 Device Boundary-Scan Port Timing Waveforms

For further information on the startup sequence, bitstream, and internal configuration registers referenced here, refer to “Configuration Sequence” in Chapter1.

Configuring through Boundary-Scan

One of the most common Boundary-Scan vendor-specific instructions is the configure instruction. If the Virtex-5 device is configured via JTAG on power-up, it is advisable to tie the mode pins to the Boundary-Scan configuration mode settings: 101 (M2 = 1, M1 = 0, M0= 1).

The configuration flow for Virtex-5 device configuration with JTAG is shown in Figure3-6. The sections that follow describe how the Virtex-5 device can be configured as a single device through the Boundary-Scan or as part of a multiple-device scan chain.

A configured device can be reconfigured by toggling the TAP and entering a CFG_IN instruction after pulsing the PROGRAM pin or issuing the shut-down sequence. (Refer to Figure3-6.)

Designers who wish to implement the Virtex-5 JTAG configuration algorithm are encouraged to use the SVF-based flow provided in Xilinx application note XAPP058.

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020