Revision History
This section provides designers with the data sheet specifications for Stratix? II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG
boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix II GX devices.
This section includes the following chapters:
■Chapter1, Introduction
■Chapter2, Stratix II GX Architecture■Chapter3, Configuration & Testing
■Chapter4, DC and Switching Characteristics■
Chapter5, Reference and Ordering Information
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.
Transceivers
capable of built-in self test (BIST) generation and verification. The ALT2GXB megafunction in the QuartusII software provides a step-by-step menu selection to configure the transceiver.
Figure2–1 shows the block diagram for the StratixIIGX transceiver channel. StratixIIGX transceivers provide PCS and PMA
implementations for all supported protocols. The PCS portion of the transceiver consists of the word aligner, lane deskew FIFO buffer, rate matcher FIFO buffer, 8B/10B encoder and decoder, byte serializer and deserializer, byte ordering, and phase compensation FIFO buffers.Each StratixII GX transceiver channel is also capable of BIST generation and verification in addition to various loopback modes. The PMA portion of the transceiver consists of the serializer and deserializer, the CRU, and the high-speed differential transceiver buffers that contain pre-emphasis, programmable on-chip termination (OCT), programmable voltage output differential (VOD), and equalization.
Transmitter Path
This section describes the data path through the Stratix II GX transmitter. The Stratix II GX transmitter contains the following modules:
■■■■■■■■
Transmitter PLLs
Access to one of two PLLs
Transmitter logic array interface
Transmitter phase compensation FIFO bufferByte serializer8B/10B encoder
Serializer (parallel-to-serial converter)Transmitter differential output buffer
Transmitter PLLs
Each transceiver block has two transmitter PLLs which receive two reference clocks to generate timing and the following clocks:
■■
High-speed clock used by the serializer to transmit the high-speeddifferential transmitter data
Low-speed clock to load the parallel transmitter data of the serializer
The serializer uses high-speed clocks to transmit data. The serializer is also referred to as parallel in serial out (PISO). The high-speed clock is fed to the local clock generation buffer. The local clock generation buffers divide the high-speed clock on the transmitter to a desired frequency on a per-channel basis. Figure2–3 is a block diagram of the transmitter clocks.
Stratix II GX Device Handbook, Volume 1
Transceivers
f
Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Handbook.
The output buffer, as shown in Figure2–8, is directly driven by the
high-speed data serializer and consists of a programmable output driver, a programmable pre-emphasis circuit, a programmable termination, and a programmable VCM.Figure2–8.Output Buffer
SerializerOutput BufferProgrammablePre-EmphasisProgrammableOutputDriverProgrammableTerminationOutputPinsProgrammable Output Driver
The programmable output driver can be set to drive out differentially 200to 1,400 mV. The differential output voltage (VOD) can be changed dynamically, or statically set by using the ALT2GXB megafunction or through I/O pins.
The output driver may be programmed with four different differential termination values:
■■■■
100 Ω120 Ω150 Ω
External termination
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Stratix II GX Device Handbook, Volume 1
Digital Signal Processing (DSP) Block
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Figure2–60.DSP Block Interface to Interconnect
C4 InterconnectDirect Link Interconnectfrom Adjacent LABR4 InterconnectDirect Link Outputsto Adjacent LABsDirect Link Interconnectfrom Adjacent LAB36DSP BlockRow StructureLAB1836LAB16161236ControlA[17..0]B[17..0]OA[17..0]OB[17..0]36Row InterfaceBlockDSP Block toLAB Row InterfaceBlock Interconnect Region36 Inputs per Row36 Outputs per RowA bus of 44 control signals feeds the entire DSP block. These signals include clocks, asynchronous clears, clock enables, signed and unsigned control signals, addition and subtraction control signals, rounding and saturation control signals, and accumulator synchronous loads. The clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for control signals, data inputs, and outputs is shown in Table2–23.
f
Refer to the DSP Blocks in Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device Handbook for more information on DSP blocks.
Stratix II GX Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP1S40F780I6N中文规格书 - 图文
