半导体传感器AD7711ARZ中文规格书

AD7705/AD7706

MICROCOMPUTER/MICROPROCESSOR INTERFACING

The flexible serial interface of the AD7705/AD7706 allows easy interfacing to most microcomputers and microprocessors. The flowchart in Figure 21 outlines the sequence to follow when interfacing a microcontroller or microprocessor to the AD7705/AD7706. Figure 22 through Figure 24 show typical interface circuits.

The serial interface is capable of operating from three wires and is compatible with SPI interface protocols. The 3-wire operation makes these parts ideal for an isolated system in which minimizing the number of interface lines minimizes the number of opto-isolators required in the system. The serial clock input is a Schmitt-triggered input to accommodate slow edges from opto-couplers. The rise and fall times of other digital inputs to the AD7705/AD7706 should be no longer than 1 μs.

Most of the registers on the AD7705/AD7706 are 8-bit registers, which facilitates easy interfacing to the 8-bit serial ports of micro-controllers. The data register on the AD7705/AD7706 is 16 bits, and the offset and gain registers are 24-bit registers, but data transfers to these registers can consist of multiple 8-bit transfers to the serial port of the microcontroller. DSP processors and microprocessors generally transfer 16 bits of data in a serial data operation. Some of these processors, such as the ADSP-2105, have the facility to program the number of cycles in a serial transfer. This allows the user to tailor the number of bits in any transfer to match the length of the required register in the AD7705/AD7706.

Because some registers on the AD7705/AD7706 are only 8 bits long, successive write operations to two of these registers can be handled as a single 16-bit data transfer. For example, to update the setup register, the processor must write to the communication register to indicate that the next operation is a write to the setup register, and then write 8 bits to the setup register. This can be done in a single 16-bit transfer, because once the eight serial clocks of the write operation to the communication register are complete, the part immediately sets up for a write operation to the setup register.

The second scheme is to use an interrupt-driven system, in which case the DRDY output is connected to the IRQ input of the 68HC11. For interfaces that require control of the CS input on the AD7705/AD7706, a port bit of the 68HC11 (such as

PC1) that is configured as an output can be used to drive the CS input.

VDDVDDSSAD7705/AD770668HC11SCKRESETSCLKMISODOUTMOSIDINCS01166-022Figure 22. AD7705/AD7706-to-68HC11 Interface

The 68HC11 is configured in master mode with its CPOL and CPHA bits set to Logic 1. When the 68HC11 is configured like this, its SCLK line idles high between data transfers. The AD7705/ AD7706 are not capable of a full duplex operation. If the AD7705/ AD7706 are configured for a write operation, no data appears on the DOUT lines, even when the SCLK input is active. Similarly, if the AD7705/AD7706 are configured for a read

operation, data presented to the part on the DIN line is ignored, even when SCLK is active.

Coding for an interface between the 68HC11 and the AD7705/ AD7706 is given in the C Code for Interfacing AD7705 to 68HC11 section. In this example, the DRDY output line of the AD7705 is connected to the PC0 port bit of the 68HC11 and is polled to determine its status.

VDDAD7705/AD7706AD7705/AD7706-to-68HC11 Interface

Figure 22 shows an interface between the AD7705/AD7706 and the 68HC11 microcontroller. The diagram shows the minimum (3-wire) interface with CS on the AD7705/AD7706 hardwired low. In this scheme, the DRDY bit of the communication register is monitored to determine when the data register is updated. An alternative scheme, which increases the number of interface lines to four, is to monitor the DRDY output line from the AD7705/ AD7706. Monitoring the DRDY line can be done in two ways. First, DRDY can be connected to a 68HC11 port bit (such as PC0) that is configured as an input. This port bit is then polled to determine the status of DRDY.

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8XC51VDDRESETP3.0DOUTDINP3.1SCLKCS01166-023Figure 23. AD7705/AD7706-to-8XC51 Interface

AD7705/AD7706

AD7705/AD7706-to-8051 Interface

An interface circuit between the AD7705/AD7706 and the 8XC51 microcontroller is shown in Figure 23. The diagram shows the minimum number of interface connections with CS on the AD7705/AD7706 hardwired low. In the case of the 8XC51

interface, the minimum number of interconnects is two. In this scheme, the DRDY bit of the communication register is monitored to determine when the data register is updated. The alternative scheme, which increases the number of interface lines to three, is to monitor the DRDY output line from the AD7705/AD7706. Monitoring the DRDY line can be done in two ways. First, DRDY can be connected to a 8XC51 port bit (such as P1.0) that is configured as an input. This port bit is then polled to determine the status of DRDY. The second scheme is to use an interrupt-driven system, in which case the DRDY output is connected to the INT1 input of the 8XC51. For interfaces that require control of the CS input on the AD7705/AD7706, a port bit of the 8XC51 (such as P1.1) that is configured as an output can be used to drive the CS input. The 8XC51 is configured in Mode 0 serial interface mode. Its serial interface contains a single data line. As a result, the DOUT and DIN pins of the AD7705/

AD7706 should be connected together with a 10 kΩ pull-up resistor. The serial clock on the 8XC51 idles high between data transfers. During a write operation, the 8XC51 outputs the LSB first. Because the AD7705/AD7706 expect the MSB first, the data must be rearranged before being written to the output serial register. Similarly, during a read operation, the AD7705/ AD7706 output the MSB first, and the 8XC51 expects the LSB first. Therefore, the data read into the serial buffer must be rearranged before the correct data-word from the AD7705/ AD7706 is available in the accumulator.

VDDAD7705/AD7706-to-ADSP-2103/ADSP-2105 Interface

Figure 24 shows an interface between the AD7705/AD7706 and the ADSP-2103/ADSP-2105 DSP processor. In the interface shown, the DRDY bit of the communication register is monitored to determine when the data register is updated. The alternative scheme is to use an interrupt-driven system, in which case the DRDY output is connected to the IRQ2 input of the ADSP-2103/ ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105 is set up for alternate framing mode. The RFS and TFS pins of the ADSP-2103/ADSP-2105 are configured as active low outputs, and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is configured as an output. The CS for the AD7705/AD7706 is active when either the RFS or TFS outputs from the ADSP-2103/ ADSP-2105 are active. The serial clock rate on the ADSP-2103/ ADSP-2105 should be limited to 3 MHz to ensure correct operation with the AD7705/AD7706.

CODE FOR SETTING UP THE AD7705/AD7706

The following section shows a set of read and write routines in C code for interfacing the 68HC11 microcontroller to the AD7705. The sample program sets up the various registers on the AD7705 and reads 1000 samples from one channel into the 68HC11. The setup conditions on the part are the same as those outlined for the flowchart of Figure 21. In the example code given here, the DRDY output is polled to determine if a new valid word is available in the data register. The same sequence is applicable for the AD7706. The sequence of events in this program are as follows: 1.

Write to the communication register, selecting Channel 1as the active channel and setting the next operation to be awrite to the clock register.

Write to the clock register, setting the CLKDIV bit, whichdivides the external clock internally by two. This assumesthat the external crystal is 4.9512 MHz. The update rate isselected to be 50 Hz.

Write to the communication register selecting Channel 1 asthe active channel and setting the next operation to be awrite to the setup register.

Write to the setup register, setting the gain to 1, settingbipolar mode, buffer off, clearing the filter

synchronization, and initiating a self-calibration.Poll the DRDY output.

Read the data from the data register.

Repeat Steps 5 and 6 (loop) until the specified number ofsamples has been taken from the selected channel.

AD7705/AD77062.

ADSP-2103/ADSP-2105RESETRFSTFSDRDOUTCS3.

DTDIN4.

SCLKSCLK01166-0245.6.7.

Figure 24. AD7705/AD7706-to-ADSP-2103/ADSP-2105 Interface

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