PROGRAM PAGE (80h-10h)
The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache reg-ister, and moves the data from the cache register to the specified block and page ad-dress in the array of the selected die (LUN). This command is accepted by the die (LUN)when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busywith a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register and move it to the NAND array at the block andpage address specified, write 80h to the command register. Unless this command hasbeen preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the 80hto the command register clears all of the cache registers' contents on the selected target.Then write n address cycles containing the column address and row address. Data inputcycles follow. Serial data is input beginning at the column address specified. At any timeduring the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR IN-TERNAL DATA INPUT (85h) commands may be issued. When data input is complete,write 10h to the command register. The selected LUN will go busy(RDY = 0, ARDY = 0) for tPROG as data is transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B#signal or, alternatively, the status operations (70h, 78h) may be used. When the die(LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit.In devices that have more than one die (LUN) per target, during and following inter-leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) commandmust be used to select only one die (LUN) for status output. Use of the READ STATUS(70h) command could cause more than one die (LUN) to respond, resulting in bus con-tention.
The PROGRAM PAGE (80h-10h) command is used as the final command of a two-planeprogram operation. It is preceded by one or more PROGRAM PAGE TWO-PLANE(80h-11h) commands. Data is transferred from the cache registers for all of the ad-dressed planes to the NAND array. The host should check the status of the operation byusing the status operations (70h, 78h).
When internal ECC is enabled, the duration of array programming time is tPROG_ECC.During tPROG_ECC, the internal ECC generates parity bits when error detection is com-plete.
Figure 44: PROGRAM PAGE (80h-10h) Operation
Cycle typeCommandAddressAddressAddressAddressAddresstADLDINDINDINDINCommandCommandDOUTI/O[7:0]80hC1C2R1R2R3D0D1…Dn10htWB tPROG_ECCtPROG or70hStatusRDYPROGRAM PAGE CACHE (80h-15h)
The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to acache register; copies the data from the cache register to the data register; then movesthe data register contents to the specified block and page address in the array of the se-lected die (LUN). After the data is copied to the data register, the cache register is availa-PDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Internal Data Move Operations
READ FOR INTERNAL DATA MOVE (00h-35h)
The READ FOR INTERNAL DATA MOVE (00h-35h) command is functionally identical tothe READ PAGE (00h-30h) command, except that 35h is written to the command regis-ter instead of 30h.
Though it is not required, it is recommended that the host read the data out of the de-vice to verify the data prior to issuing the PROGRAM FOR INTERNAL DATA MOVE(85h-10h) command to prevent the propagation of data errors.
If internal ECC is enabled, the data does not need to be toggled out by the host to becorrected and moving data can then be written to a new page without data reloading,which improves system performance.
Figure 50: READ FOR INTERNAL DATA MOVE (00h-35h) Operation
Cycle type
CommandAddressAddressAddressAddressAddressCommandDOUTDOUTDOUTI/O[7:0]RDY
00hC1C2R1R2R335htWBtRtRRDnDn+1Dn+2Figure 51: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h)
Cycle typeCommandAddressAddressAddressAddressAddressCommandDOUTDOUTDOUTI/O[7:0]RDY00hC1C2R1R2R335htWBtRtRRD0…Dj + n1Cycle typeCommandAddressAddressCommandtWHRDOUTDOUTDOUTI/O[7:0]RDY05hC1C2E0hDkDk + 1Dk + 21PDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Block Lock Feature
Figure 62: PROGRAM/ERASE Issued to Locked Block
tLBSYR/B#I/OxPROGRAM or ERASEAddress/data inputLocked blockCONFIRM70hREAD STATUS60hBLOCK LOCK READ STATUS (7Ah)
The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protectionstatus of individual blocks. The address cycles have the same format, as shown below,and the invert area bit should be set LOW. On the falling edge of RE# the I/O pins outputthe block lock status register, which contains the information on the protection statusof the block.
Table 20: Block Lock Status Register Bit Definitions
Block Lock Status Register DefinitionsBlock is locked tightBlock is lockedBlock is unlocked, and device is locked tightBlock is unlocked, and device is not locked tightI/O[7:3]XXXXI/O2 (Lock#)0011I/O1 (LT#)0101I/O0 (LT)1010Figure 63: BLOCK LOCK READ STATUS
CLECE#WE#tWHRALERE#I/Ox7AhBLOCK LOCKREAD STATUS
Add 1Add 2Add 3StatusBlock address
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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash MemoryOne-Time Programmable (OTP) Operations
OTP DATA READ (00h-30h)
To read data from the OTP area, set the device to OTP operation mode, then issue thePAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP areawhether the area is protected or not.
To use the PAGE READ command for reading data from the OTP area, issue the 00hcommand, and then issue five address cycles: for the first two cycles, the column ad-dress; and for the remaining address cycles, select a page in the range of 02h-00h-00hthrough 1Fh-00h-00h. Lastly, issue the 30h command. The PAGE READ CACHE MODEcommand is not supported on OTP pages.
R/B# goes LOW (tR) while the data is moved from the OTP page to the data register. TheREAD STATUS (70h) command is the only valid command for reading status in OTP op-eration mode. Bit 5 of the status register reflects the state of R/B# (see Status Opera-tions).
Normal READ operation timings apply to OTP read accesses. Additional pages withinthe OTP area can be selected by repeating the OTP DATA READ command.
The PAGE READ command is compatible with the RANDOM DATA OUTPUT (05h-E0h)command.
Only data on the current page can be read. Pulsing RE# outputs data sequentially.
Figure 68: OTP DATA READ
CLECE#WE#ALEtRRE#Coladd 1Coladd 2OTPpage1OTP addressR/B#Don’t CareDOUTnDOUTn + 1DOUTmI/Ox00h00h00h30hBusyNote:1.The OTP page must be within the 02h–1Fh range.
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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Two-Plane Operations
Figure 77: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT
tRR/B#I/Ox00hAddress (5 cycles)1st-plane source00hAddress (5 cycles)2nd-plane source35h85hAddress (5 cycles)Data85hAddress (2 cycles)Unlimited numberof repetitionsData11h1st-plane destinationOptional1PDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
MEMORY存储芯片MT48H16M32L2B5-8中文规格书 - 图文
