Pin Definitions
Table1-12 lists the pin definitions used in 7series FPGAs packages.
Note:There are dedicated general purpose user I/O pins listed separately in Table1-12. There are
also multi-function pins where the pin names start with either IO_LXXY_ZZZ_# or IO_XX_ZZZ_#, where ZZZ represents one or more functions in addition to being general purpose user I/O. If not used for their special function, these pins can be user I/O.
IMPORTANT:For Tandem PROM configuration, the configuration PERSIST property is required. In this case, a dual-purpose I/O that is used for stage 1 and stage 2 configuration cannot be repurposed as user I/O after stage 2 configuration is complete.
Table 1-12:7Series FPGAs Pin Definitions
Type
Direction
Description
Most user I/O pins are capable of differential signaling and can be implemented as pairs. The top and bottom I/O pins are always single ended. Each user I/O is labeled IO_LXXY_#, where:
°°
Pin NameUser I/O Pins
IO_LXXY_#IO_XX_#
Dedicated
Input/Output
IO indicates a user I/O pin
L indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair# indicates a bank number
°
Configuration Pins
For more information, see the Configuration Pin Definitions table in UG470, 7Series FPGAs Configuration User Guide.CCLK_0DONE_0INIT_B_0
M0_0, M1_0, or M2_0PROGRAM_B_0TCK_0TDI_0TDO_0TMS_0
Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)
Input/OutputBidirectional
Configuration clock. Output in Master mode or input in Slave mode
DONE indicates successful completion of configuration (active High)
Bidirectional Indicates initialization of configuration memory (active (open-drain)Low)
InputInputInputInputOutputInput
Configuration mode selection
Asynchronous reset to configuration logic (active Low)JTAG clockJTAG data inputJTAG data outputJTAG mode select
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
X-Ref Target - Figure 3-1221A2345678910111213141516171819202122232425262728293011711717171717171616161616ABCDEFGHJKL1161161161161161161161161161161161161161161161161151151151151151151151151141141141141141141141141141141141141131131131131131131131131121121121121121121121121121121121121121121121123456117117117117117117117117117117117117117117B116116CD116116EF115115GH115115JK115115LM115115NP114114RT114114UV114114WY113113AAAB113113ACAD113113AEAF113113AGAH112112AJAK1121121217171711711717171616161616161616171717171717161616161717171616161616161616161171171717171717171616161717171716161616171717171716161616161616161717171711511517171616161617171716161616161515151517171717115115171717151515151515151515151515151515115115151515151515151515M1515NPRTUVWY15151515151515151515151141141515151515151515141514141414141414141414141414141414141414141131131414141414141414141414141414141414141414141414113113141414141414131212131313131313131213131312121212121313131313AA1212131313131313AB1313ACAD121212131313131212121212121213131312121212131313AE13AF12121212121212131312121212121213131313AG1313AHAJ1212121312121212127891213131312121212131313AK101112131415161718192021222324252627282930ug475_c3_38_052311Figure 3-122:FF901, FFG901, and FFV901 Packages—XC7K355T I/O Banks
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
X-Ref Target - Figure 3-1241ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAK123456789101112131415161718192021222324252627282930171817171818171700151515151414141413121111121211111211111212131213131314141518171516161616161616ABCDEFGHJKLMNPRTUVWYAAABAC13ADAEAFAGAHAJAK23456789101112131415161718192021222324252627282930Power Pins#VCCO_#VCCINTVCCAUX#VCCAUX_IO_G#VCCBRAMVCCBATT_0VCCADC_0GNDADC_0###MGTVCCAUXMGTVCCAUX_G# or MGTHVCCAUX_G#MGTAVCCMGTAVCC_G# or MGTHAVCC_G#MGTAVTTMGTAVTT_G# or MGTHAVTT_G#GNDug475_c3_40_052311Figure 3-124:FF901, FFG901, and FFV901 Packages—XC7K355T Power and GND Placement
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
FF1156, FFG1156, and FFV1156 Packages—XC7K420T and
XC7K480T
X-Ref Target - Figure 3-1291ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAP12345678910111213141516171819202122232425262728293031323334AEBCECDEEOKIMssssFGHJKVVVVVVVVEEEVVEVEEVEGsSSSSJsVEVEsEVEVVEVEEEVVVVE4567GVRNVRPVREFD00?D31A00?A28DQSMRCCSRCCEVVVLsssYD2s10sVEP89ssBLMNPVrBrBRTUBBVWVBBUBYAAABACADAEAFVssVAGAHAJAKALAMANAPV2310111213141516171819202122232425262728293031323334User I/O PinsIO_LXXY_#sIO_XX_#Transceiver PinsEVMGTAVCC_G#MGTAVTT_G#MGTVCCAUX_G#MGTAVTTRCALMGTRREFMGTREFCLK1/0PMGTREFCLK1/0NMGTXRXPMGTXRXNMGTXTXPMGTXTXNMGTHAVCC_G#MGTHAVTT_G#MGTHRXPMGTHRXNMGTHTXPMGTHTXNY012PKIOMDJLCDedicated PinsCCLK_0CFGBVS_0DONE_0DXP_0DXN_0GNDADC_0INIT_B_0M0_0M1_0M2_0PROGRAM_B_0TCK_0TDI_0TDO_0TMS_0VCCADC_0VCCBATT_0nSSSSVP_0VN_0VREFP_0VREFN_0Other PinsGNDVCCAUX_IO_G#VCCAUXVCCINTVCCO_#VCCBRAMNCMulti?Function PinsBBBBBBBBUrADV_BFCS_BFOE_BMOSIFWE_BDOUT_CSO_BCSI_BPUDC_BRDWR_BRS0?RS1AD0P/AD0N?AD15P/AD15NEMCCLKVug475_c3_53_090511Figure 3-129:FF1156, FFG1156, and FFV1156 Packages—XC7K420T and XC7K480T Pinout Diagram
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
Virtex-7 FPGAs Device Diagrams
Table 3-4:Device
XC7V585TXC7V2000T
Virtex-7T FPGAs Device Diagrams Cross ReferenceFF1157FFG1157RF1157
page170
FF1761FFG1761RF1761
page174
FL1925FLG1925FH1761 FHG1761
page178page182
Table 3-5:Device
XC7VX330TXC7VX415TXC7VX485TXC7VX550TXC7VX690TXC7VX980T
Virtex-7XT FPGAs Device Diagrams Cross ReferenceFF1157FFG1157FFV1157RF1157
page186
page186page194
page202page206page210
page194
FF1158FFG1158FFV1158RF1158FF1761FF1927 FF1930FFG1761FF1926FF1928FL1926FL1928FL1930
FFG1927FFG1930FFV1761FFG1926FFG1928FLG1926FLG1928FLG1930FFV1927RF1930
RF1761
page190
page198page214page230
page234
page238page242
page246page250page254
page218
page186page194page222page226page230
page226
XC7VX1140T
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
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7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
FPGA可编程逻辑器件芯片XCZU3EG-L1SFVC784I中文规格书 - 图文
