Table1–25.True & Emulated LVDS Specifications(Note1), (2)(Part 3 of 3)
Symbol
Non DPA ModeSampling Window
Notes to Table1–25:
(1)When J = 3 to 10, the SERDES block is used.(2)When J = 1 or 2, the SERDES block is bypassed.
(3)Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4)The minimum and maximum specification is dependent on the clock source (PLL and clock pin, for example) and the clock routing resource (global, regional, or
local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate.(5)The txJitter specification is for true LVDS IO standard only.
(6)You can estimate the achievable maximum data rate for non-DPA mode by performing the link timing closure analysis. You should consider the board skew margin,
transmitter delay margin as well as the receiver sampling margin to determine the maximum data rate supported.(7)This is achieved by using the LVDS and DPA clock network.
(8)If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150Mbps.
MaxMaxMax———300——300——300——300
MaxMinMinMinMinTypTypTypTypConditions
Table1–26.StratixIII DPA Lock Time Specifications (Note1), (2), (3) (Part 1 of 2)
Number of
Number of
Data
repetitions
Transitions
per 256
in one
data
repetition
transition
of training
(4)
pattern
Standard
Training Pattern
Condition (5)MinTypMax
SPI-4
00000000001111111111
without DPA PLL calibration
2
128
with DPA PLL calibrationwithout DPA PLL calibration
256 data transitions3×256 data transitions + 2×96 slow clock cycles
(6)256 data transitions3×256 data transitions + 2×96 slow clock cycles
(6)256 data transitions3×256 data transitions + 2×96 slow clock cycles
(6)
——————
——————
00001111
Parallel Rapid I/O
10010000
2128
with DPA PLL calibrationwithout DPA PLL calibration
464
with DPA PLL calibration
Stratix III Device Handbook, Volume 2
Unitps
C2C3, I3C4, I4C4L, I4L
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsSwitching Characteristics
Table1–29.StratixIII Maximum Clock Rate Support for External Memory Interfaces with Full-Rate Controller(Note1), (2), (3), (4)
Memory StandardsDDR2 SDRAM (5)DDR SDRAM
Notes to Table1–29:
(1)The supported operating frequencies listed here are memory interface maximums for the FPGA device family. Your design’s actual achievable
performance is based on design- and system-specific factors, as well as static timing analysis of the completed design.(2)This performance specification applies for interfaces with single rank unregistered DIMMs and single chip-select discrete components. For
more information on a list of other supported configurations and corresponding performance specifications, refer to the External Memory PHY Interface (ALTMEMPHY) Megafunction User Guide.(3)The values apply to column I/Os, Rows I/Os and Hybrid mode interface. Column I/Os refers to Top and Bottom I/Os. Row I/Os refers to Left and
Right I/Os. Hybrid mode refers to DQ/DQS groups wrapping over Column I/Os and Row I/Os of the device. (4)It may be possible to close timing at up to 33MHz higher, depending on your design and the Quartus setting used. Refer to the section on
advanced settings in External Memory PHY Interface (ALTMEMPHY) Megafunction User Guide.(5)We recommend use of ALTMEMPHY AFI mode to achieve these quoted maximum clock rate due to lower performance of Non-AFI mode.
C2VCCL = 1.1V300200
C3, I3VCCL = 1.1V267200
C4, I4VCCL = 1.1V233200
C4L, I4L
VCCL = 1.1V233200
VCCL = 0.9V167167
UnitMHzMHz
External Memory I/O Timing Specifications
Table1–30 and Table1–31 list StratixIII device timing uncertainties on the read and write data paths. Use these specifications to determine timing margins for source synchronous paths between the StratixIII FPGA and the external memory device. Refer to the figure for “SW (sampling window)” in “Glossary”
.
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table1–30.Sampling Window (SW) - Read Side (Note1) (Part 2 of 2)
C2
Memory Type
I/O Standard
Width
VCCL = 1.1VSW (ps)Setup
QDRII/II+ SRAMQDRII/II+ SRAM Emulation (2) RLDRAM IIRLDRAM II
Notes to Table1–30:.
(1)The values apply to Column I/Os, Row I/Os and Hybrid mode interface. Column I/Os refer to Top and Bottom I/Os. Hybrid mode refers to DQ/DQS groups
wrapping over Column I/Os and Row I/Os of the device.(2)Please refer to the section “Supporting ×36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packages” on page8–20 in chapter 8 External Memory
Interface in StratixIII Devices for the implementation.
C3, I3VCCL = 1.1VSW (ps)Setup314314264264
Hold291337356356
C4, I4VCCL = 1.1VSW (ps)Setup337337287287
Hold291350356356
C4L, I4LVCCL = 1.1VSW (ps)Setup337337287287
Hold291350356356
C4L, I4LVCCL = 0.9VSW (ps)Setup337337287287
Hold291350356356
Hold286328336336
1.8 V HSTL1.8 V HSTL1.5 V HSTL1.8 V HSTL
×9, ×18, ×36×36×9, ×18×9, ×18
261261211211
Table1–31.Transmitter Channel-to-Channel Skew (TCCS) - Write Side (Note1)(Part 1 of 2)
C2
Memory Type
I/O Standard
Width
VCCL = 1.1VTCCS (ps)Lead
DDR3 SDRAM (with Deskew circuitry, 401MHz–533MHz)DDR3 SDRAM(8-tap phase offset, 375MHz-400MHz)
DDR3 SDRAM (8-tap phase offset, 360MHz-375MHz)
DDR3 SDRAM(10-tap phase offset, 333MHz-360MHz)
DDR3 SDRAM(10-tap phase offset, 300MHz-333MHz)
DDR2 SDRAM Differential DQS
DDR2 SDRAM Single-ended DQS
1.5V SSTL1.5V SSTL1.5V SSTL1.5V SSTL1.5V SSTL1.8V SSTL1.8V SSTL
×4,×8
253
Lag262
C3, I3VCCL = 1.1VTCCS (ps)Lead—
Lag—
C4, I4VCCL = 1.1VTCCS (ps)Lead—
Lag—
C4L, I4LVCCL = 1.1VTCCS (ps)Lead—
Lag—
C4L, I4LVCCL = 0.9VTCCS (ps)Lead—
Lag—
×4, ×8293284341332——————
×4, ×8293284341373——————
×4, ×8169470217496258528258528——
×4, ×8169470217496258528258528——
×4, ×8×4, ×8
229316
246168
230318
355239
250346
388260
250346
388260
350446
488360
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table1–44.EP3SL50 Row Pins Input Timing Parameters (Part 3 of 3)
ParameterI/O Standard
Fast ModelIndustrial-0.8300.9441.040-0.790-0.8440.9581.026-0.776-0.8440.9581.026-0.776-0.8300.9441.040-0.790-0.8300.9441.040-0.790-0.8210.9351.049-0.799-0.8210.9351.049-0.799-0.8901.0030.904-0.655-0.8901.0030.904-0.655
Commercial-0.8710.9981.036-0.774-0.8831.0101.024-0.762-0.8831.0101.024-0.762-0.8710.9981.036-0.774-0.8710.9981.036-0.774-0.8590.9861.048-0.786-0.8590.9861.048-0.786-0.9251.0510.906-0.645-0.9251.0510.906-0.645
C2
VCCL=1.1V
C3
VCCL=1.1V
C4
VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3
VCCL=1.1V
I4
VCCL=1.1V
VCCL=1.1V
I4L
VCCL=0.9V
ClockUnitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
GCLK
SSTL-15 CLASS I
tsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuthtsuth
-1.213-1.321-1.434-1.378-1.646-1.331-1.444-1.390-1.6821.3991.707
1.5261.940
1.6622.164
1.5932.050
1.8582.077
1.5461.942
1.6812.166
1.6162.049
1.8932.123
GCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLK
-1.309-1.493-1.666-1.582-1.604-1.488-1.658-1.571-1.649-1.228-1.331-1.452-1.396-1.664-1.342-1.461-1.407-1.6991.4131.692
1.5361.930
1.6802.146
1.6112.032
1.8762.059
1.5571.931
1.6982.149
1.6332.032
1.9102.106
1.8-V HSTL CLASS I
-1.295-1.483-1.648-1.564-1.586-1.477-1.641-1.554-1.632-1.228-1.331-1.452-1.396-1.664-1.342-1.461-1.407-1.6991.4131.692
1.5361.930
1.6802.146
1.6112.032
1.8762.059
1.5571.931
1.6982.149
1.6332.032
1.9102.106
1.8-V HSTL CLASSII
-1.295-1.483-1.648-1.564-1.586-1.477-1.641-1.554-1.632-1.213-1.321-1.434-1.378-1.646-1.331-1.444-1.390-1.6821.3991.707
1.5261.940
1.6622.164
1.5932.050
1.8582.077
1.5461.942
1.6812.166
1.6162.049
1.8932.123
1.5-V HSTL CLASS I
-1.309-1.493-1.666-1.582-1.604-1.488-1.658-1.571-1.649-1.213-1.321-1.434-1.378-1.646-1.331-1.444-1.390-1.6821.3991.707
1.5261.940
1.6622.164
1.5932.050
1.8582.077
1.5461.942
1.6812.166
1.6162.049
1.8932.123
1.5-V HSTL CLASSII
-1.309-1.493-1.666-1.582-1.604-1.488-1.658-1.571-1.649-1.204-1.311-1.418-1.362-1.630-1.322-1.428-1.374-1.6661.3901.716
1.5161.950
1.6462.180
1.5772.066
1.8422.093
1.5371.951
1.6652.182
1.6002.065
1.8772.139
1.2-V HSTL CLASS I
-1.318-1.503-1.682-1.598-1.620-1.497-1.674-1.587-1.665-1.204-1.311-1.418-1.362-1.630-1.322-1.428-1.374-1.6661.3901.716
1.5161.950
1.6462.180
1.5772.066
1.8422.093
1.5371.951
1.6652.182
1.6002.065
1.8772.139
1.2-V HSTL CLASSII
-1.318-1.503-1.682-1.598-1.620-1.497-1.674-1.587-1.665-1.288-1.413-1.637-1.583-1.845-1.427-1.644-1.593-1.8801.4731.557
1.6201.773
1.8671.921
1.7991.805
2.0601.831
1.6441.769
1.8831.926
1.8191.772
2.0951.880
3.0-V PCI
GCLK PLLGCLK
3.0-V PCI-X
-1.160-1.324-1.421-1.336-1.355-1.313-1.416-1.292-1.402-1.288-1.413-1.637-1.583-1.845-1.427-1.644-1.593-1.8801.4731.557
1.6201.773
1.8671.921
1.7991.805
2.0601.831
1.6441.769
1.8831.926
1.8191.772
2.0951.880
GCLK PLL
-1.160-1.324-1.421-1.336-1.355-1.313-1.416-1.292-1.402
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table1–45.EP3SL50 Column Pins output Timing Parameters (Part 4 of 7)
ParameterI/O Standard
Current StrengthFast ModelIndustrialCommercial3.1081.6742.9861.5512.9331.4972.9121.4772.9261.4912.9291.4942.9101.4752.9051.4702.9441.5092.9251.4902.9261.4912.9091.4742.9051.470
3.3411.8693.2061.7333.1651.6923.1311.6583.1391.6663.1421.6693.1221.6493.1151.6423.1591.6863.1381.6663.1411.6683.1211.6483.1171.645
C2
VCCL=1.1V
C3
VCCL=1.1V
C4
VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3
VCCL=1.1V
I4
VCCL=1.1V
VCCL=1.1V
I4L
VCCL=0.9V
ClockGCLK
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
tco4.7682.4664.5492.2464.4732.1704.4342.1314.4422.1384.4462.1424.4252.1204.4102.1054.4652.1614.4432.1394.4512.1474.4272.1234.4232.119
5.1715.6845.5512.5882.8412.8464.9405.4445.3112.3552.6172.6224.8635.3705.2372.2792.5632.5684.8205.3205.1872.2362.5282.5334.8285.3285.1952.2432.5202.5254.8325.3325.1992.2472.5262.5314.8105.3105.1772.2262.4992.5044.7945.2935.1602.2092.4972.5024.8515.3515.2182.2662.5502.5554.8295.3295.1962.2442.5262.5314.8385.3395.2062.2532.5462.5514.8135.3145.1812.2282.5212.5264.8095.3095.1762.2242.5162.521
5.7792.7875.5392.5635.4652.5095.4152.4745.4232.4665.4272.4725.4052.4455.3882.4435.4462.4965.4242.4725.4342.4925.4092.4675.4042.462
5.3042.7095.0652.4694.9902.3944.9412.3454.9472.3494.9502.3534.9292.3324.9122.3154.9702.3734.9482.3514.9582.3614.9322.3354.9282.331
5.8182.9495.5702.6985.4972.6255.4402.5695.4452.5735.4492.5775.4272.5555.4102.5375.4692.5965.4462.5745.4572.5855.4322.5605.4282.556
5.6885.8632.9532.7725.4405.6152.7022.5215.3675.5422.6292.4485.3105.4852.5732.3925.3155.4902.5772.3965.3195.4942.5812.4005.2975.4722.5592.3785.2805.4552.5412.3605.3395.5142.6002.4195.3165.4912.5782.3975.3275.5022.5892.4085.3025.4772.5642.3835.2985.4732.5602.379
2mA
GCLK
tco
PLLGCLK
tco
4mA
1.2 V
6mA
GCLK
tco
PLLGCLK
tco
GCLK
tco
PLLGCLK
tco
8mA
GCLK
tco
PLLGCLK
tco
8mA
GCLK
tco
PLLGCLK
tco
SSTL-2 CLASS I
10mA
GCLK
tco
PLLGCLK
tco
12mA
GCLK
tco
PLLGCLK
tco
SSTL-2 CLASSII
16mA
GCLK
tco
PLLGCLK
tco
4mA
GCLK
tco
PLLGCLK
tco
6mA
GCLK
tco
PLLGCLK
tco
SSTL-18 CLASS I
8mA
GCLK
tco
PLLGCLK
tco
10mA
GCLK
tco
PLLGCLK
tco
12mA
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S25B672I7中文规格书 - 图文
