TMS320C6745,TMS320C6747
SPRS377F–SEPTEMBER2008–REVISEDJUNE2014
6.8General-PurposeInput/Output(GPIO)
TheGPIOperipheralprovidesgeneral-purposepinsthatcanbeconfiguredaseitherinputsoroutputs.Whenconfiguredasanoutput,awritetoaninternalregistercancontrolthestatedrivenontheoutputpin.Whenconfiguredasaninput,thestateoftheinputisdetectablebyreadingthestateofaninternalregister.Inaddition,theGPIOperipheralcanproduceCPUinterruptsandEDMAeventsindifferentinterrupt/eventgenerationmodes.TheGPIOperipheralprovidesgenericconnectionstoexternaldevices.TheGPIOpinsaregroupedintobanksof16pinsperbank(i.e.,bank0consistsofGPIO[0:15]).
TheC6745/6747GPIOperipheralsupportsthefollowing:
?Upto128PinsonZKBandupto109PinsonPTPpackageconfigurableasGPIO?ExternalInterruptandDMArequestCapability
–EveryGPIOpinmaybeconfiguredtogenerateaninterruptrequestondetectionofrisingand/orfallingedgesonthepin.
–Theinterruptrequestswithineachbankarecombined(logicalor)tocreateeightuniquebanklevelinterruptrequests.
–ThebanklevelinterruptserviceroutinemaypolltheINTSTATxregisterforitsbanktodeterminewhichpin(s)havetriggeredtheinterrupt.
–GPIOBanks0,1,2,3,4,5,6,and7InterruptsassignedtoDSPEvents65,41,49,52,54,59,62and72respectively
–Additionally,GPIOBanks0,1,2,3,4,and5InterruptsassignedtoEDMAevents6,7,22,23,28,and29respectively.
?Set/clearfunctionality:Firmwarewrites1tocorrespondingbitposition(s)tosetortoclearGPIOsignal(s).ThisallowsmultiplefirmwareprocessestotoggleGPIOoutputsignalswithoutcriticalsectionprotection(disableinterrupts,programGPIO,re-enableinterrupts,topreventcontextswitchingtoantherprocessduringGPIOprogramming).?SeparateInput/Outputregisters
?Outputregisterinadditiontoset/clearsothat,ifpreferredbyfirmware,someGPIOoutputsignalscanbetoggledbydirectwritetotheoutputregister(s).
?Outputregister,whenread,reflectsoutputdrivestatus.This,inadditiontotheinputregisterreflectingpinstatusandopen-drainI/Ocell,allowswiredlogicbeimplemented.ThememorymapfortheGPIOregistersisshowninTable6-8.SeetheTMS320C6745/C6747DSPPeripheralsOverviewReferenceGuide.(SPRUFK9)formoredetails.
6.8.1GPIORegisterDescription(s)
Table6-8.GPIORegisters
BYTEADDRESS0x01E260000x01E260040x01E260080x01E260100x01E260140x01E260180x01E2601C0x01E260200x01E260240x01E260280x01E2602C0x01E26030
ACRONYM
REV-BINTENDIR01OUT_DATA01SET_DATA01CLR_DATA01IN_DATA01SET_RIS_TRIG01CLR_RIS_TRIG01SET_FAL_TRIG01CLR_FAL_TRIG01
GPIOBANKS0AND1
GPIOBanks0and1DirectionRegisterGPIOBanks0and1OutputDataRegisterGPIOBanks0and1SetDataRegisterGPIOBanks0and1ClearDataRegisterGPIOBanks0and1InputDataRegister
GPIOBanks0and1SetRisingEdgeInterruptRegisterGPIOBanks0and1ClearRisingEdgeInterruptRegisterGPIOBanks0and1SetFallingEdgeInterruptRegisterGPIOBanks0and1ClearFallingEdgeInterruptRegister
79
REGISTERDESCRIPTIONPeripheralRevisionRegister
Reserved
GPIOInterruptPer-BankEnableRegister
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