MSP430x13x, MSP430x14x, MSP430x14x1MIXED SIGNAL MICROCONTROLLERSLAS272F ? JULY 2000 ? REVISED JUNE 2004flash memoryThe flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. TheCPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:DFlash memory has n segments of main memory and two segments of information memory (A and B) of 128bytes each. Each segment in main memory is 512 bytes in size.DSegments 0 to n may be erased in one step, or each segment may be individually erased.DSegments A and B can be erased individually, or as a group with segments 0?n.Segments A and B are also called information memory.DNew devices may have some bytes programmed in the information memory (needed for test duringmanufacturing). The user should perform an erase of the information memory prior to the first use.8 KB0FFFFh0FE00h0FDFFh0FC00h0FBFFh0FA00h0F9FFh16 KB0FFFFh0FE00h0FDFFh0FC00h0FBFFh0FA00h0F9FFh32 KB0FFFFh0FE00h0FDFFh0FC00h0FBFFh0FA00h0F9FFh48 KB0FFFFh0FE00h0FDFFh0FC00h0FBFFh0FA00h0F9FFh60 KB0FFFFh0FE00h0FDFFh0FC00h0FBFFh0FA00h0F9FFhSegment 0w/ Interrupt VectorsSegment 1 Segment 2MainMemory0E400h0E3FFh0E200h0E1FFh0E000h010FFh01080h0107Fh01000h0C400h0C3FFh0C200h0C1FFh0C000h010FFh01080h0107Fh01000h08400h083FFh08200h081FFh08000h010FFh01080h0107Fh01000h04400h043FFh04200h041FFh04000h010FFh01080h0107Fh01000h01400h013FFhSegment n-101200h011FFhSegment n01100h010FFhSegment A01080h0107FhSegment B01000hInformationMemory16POST OFFICE BOX 655303 DALLAS, TEXAS 75265?MSP430x13x, MSP430x14x, MSP430x14x1MIXED SIGNAL MICROCONTROLLERSLAS272F ? JULY 2000 ? REVISED JUNE 2004peripheralsPeripherals are connected to the CPU through data, address, and control busses and can be handled usingall instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature numberSLAU049.digital I/OThere are six 8-bit I/O ports implemented—ports P1 through P6:DDDDAll individual I/O bits are independently programmable.Any combination of input, output, and interrupt conditions is possible.Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.Read/write access to port-control registers is supported by all instructions.oscillator and system clockThe clock system in the MSP430x13x and MSP43x14x(1) family of devices is supported by the basic clockmodule that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator(DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirementsof both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock sourceand stabilizes in less than 6 μs. The basic clock module provides the following clock signals:DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.DMain clock (MCLK), the system clock used by the CPU.DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.watchdog timerThe primary function of the watchdog timer (WDT) module is to perform a controlled system restart after asoftware problem occurs. If the selected time interval expires, a system reset is generated. If the watchdogfunction is not needed in an application, the module can be configured as an interval timer and can generateinterrupts at selected time intervals.hardware multiplier (MSP430x14x and MSP430x14x1 Only)The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplicationas well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessedimmediately after the operands have been loaded into the peripheral registers. No additional clock cycles arerequired.USART0The MSP430x13x and the MSP430x14x(1) have one hardware universal synchronous/asynchronous receivetransmit (USART0) peripheral module that is used for serial data communication. The USART supportssynchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-bufferedtransmit and receive channels.USART1 (MSP430x14x and MSP430x14x1 Only)The MSP430x14x(1) has a second hardware universal synchronous/asynchronous receive transmit (USART1)peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.Operation of USART1 is identical to USART0.POST OFFICE BOX 655303 DALLAS, TEXAS 75265?17MSP430x13x, MSP430x14x, MSP430x14x1MIXED SIGNAL MICROCONTROLLERSLAS272F ? JULY 2000 ? REVISED JUNE 2004 comparator_AThe primary function of the comparator_A module is to support precision slope analog?to?digital conversions,battery?voltage supervision, and monitoring of external analog signals.ADC12 (Not implemented in the MSP430x14x1)The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SARcore, sample select control, reference generator and a 16 word conversion-and-control buffer. Theconversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored withoutany CPU intervention.timer_A3Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiplecapture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters.Timer_A3 Signal ConnectionsInput Pin Number12 - P1.0Device Input SignalTACLKACLKSMCLK21 - P2.113 - P1.122 - P2.2TAINCLKTA0TA0DVSSDVCC14 - P1.2TA1CAOUT (internal)DVSSDVCC15 - P1.3TA2ACLK (internal)DVSSDVCCModule Input NameTACLKACLKSMCLKINCLKCCI0ACCI0BGNDVCCCCI1ACCI1BGNDVCCCCI2ACCI2BGNDVCCCCR2TA2CCR1TA1CCR0TA013 - P1.117 - P1.527 - P2.714 - P1.218 - P1.623 - P2.3ADC12 (internal)15 - P1.319 - P1.724 - P2.4TimerNAModule BlockModule Output SignalOutput Pin Numbertimer_B3 (MSP430x13x Only)Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiplecapture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters.18POST OFFICE BOX 655303 DALLAS, TEXAS 75265?MSP430x13x, MSP430x14x, MSP430x14x1MIXED SIGNAL MICROCONTROLLERSLAS272F ? JULY 2000 ? REVISED JUNE 2004timer_B7 (MSP430x14x and MSP430x14x1 Only)Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiplecapture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters.Timer_B3/B7 Signal Connections?Input Pin Number43 - P4.7Device Input SignalTBCLKACLKSMCLK43 - P4.736 - P4.036 - P4.0TBCLKTB0TB0DVSS37 - P4.137 - P4.1DVCCTB1TB1DVSS38 - P4.238 - P4.2DVCCTB2TB2DVSS39 - P4.339 - P4.3DVCCTB3TB3DVSS40 - P4.440 - P4.4DVCCTB4TB4DVSS41 - P4.541 - P4.5DVCCTB5TB5DVSS42 - P4.6DVCCTB6ACLK (internal)DVSSDVCCModule Input NameTBCLKACLKSMCLKINCLKCCI0ACCI0BGNDVCCCCI1ACCI1BGNDVCCCCI2ACCI2BGNDVCCCCI3ACCI3BGNDVCCCCI4ACCI4BGNDVCCCCI5ACCI5BGNDVCCCCI6ACCI6BGNDVCCCCR6TB6CCR5TB5CCR4TB4CCR3TB3CCR2TB2CCR1TB1CCR0TB036 - P4.0ADC12 (internal)TimerNAModule BlockModule Output SignalOutput Pin Number37 - P4.1ADC12 (internal)38 - P4.239 - P4.340 - P4.441 - P4.542 - P4.6?Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).POST OFFICE BOX 655303 DALLAS, TEXAS 75265?19MSP430x13x, MSP430x14x, MSP430x14x1MIXED SIGNAL MICROCONTROLLERSLAS272F ? JULY 2000 ? REVISED JUNE 2004peripheral file mapPERIPHERALS WITH WORD ACCESSWatchdogTimer_B7/Timer_B3(see Note 1)Watchdog Timer controlTimer_B interrupt vectorTimer_B controlCapture/compare control 0Capture/compare control 1Capture/compare control 2Capture/compare control 3Capture/compare control 4Capture/compare control 5Capture/compare control 6Timer_B registerCapture/compare register 0Capture/compare register 1Capture/compare register 2Capture/compare register 3Capture/compare register 4Capture/compare register 5Capture/compare register 6Timer_A3Timer_A interrupt vectorTimer_A controlCapture/compare control 0Capture/compare control 1Capture/compare control 2ReservedReservedReservedReservedTimer_A registerCapture/compare register 0Capture/compare register 1Capture/compare register 2ReservedReservedReservedReservedHardwareMultiplier(MSP430x14x andMSP430x14x1only)Sum extendResult high wordResult low wordSecond operandMultiply signed +accumulate/operand1Multiply+accumulate/operand1Multiply signed/operand1Multiply unsigned/operand1SUMEXTRESHIRESLOOP2MACSMACMPYSMPYTARTACCR0TACCR1TACCR2WDTCTLTBIVTBCTLTBCCTL0TBCCTL1TBCCTL2TBCCTL3TBCCTL4TBCCTL5TBCCTL6TBRTBCCR0TBCCR1TBCCR2TBCCR3TBCCR4TBCCR5TBCCR6TAIVTACTLTACCTL0TACCTL1TACCTL20120h011Eh0180h0182h0184h0186h0188h018Ah018Ch018Eh0190h0192h0194h0196h0198h019Ah019Ch019Eh012Eh0160h0162h0164h0166h0168h016Ah016Ch016Eh0170h0172h0174h0176h0178h017Ah017Ch017Eh013Eh013Ch013Ah0138h0136h0134h0132h0130hNOTE 1:Timer_B7 in MSP430x14x(1) family has 7 CCRs, Timer_B3 in MSP430x13x family has 3 CCRs.20POST OFFICE BOX 655303 DALLAS, TEXAS 75265?
MSP430F149 - 图文
