SymbolMGTAVCCPLLMGTAVTTTXMGTAVTTRXMGTAVCCMGTAVTTRXCNotes:
1.
Description
Analog supply voltage for the GTP_DUAL shared PLL relative to GNDAnalog supply voltage for the GTP_DUAL transmitters relative to GNDAnalog supply voltage for the GTP_DUAL receivers relative to GNDAnalog supply voltage for the GTP_DUAL common circuits relative to GNDAnalog supply voltage for the resistor calibration circuit of the GTP_DUAL column
–0.5 to 1.32–0.5 to 1.32–0.5 to 1.32–0.5 to 1.1–0.5 to 1.32
UnitsVVVVV
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Table 25:Recommended Operating Conditions for GTP_DUAL Tiles(1)(2)
SymbolMGTAVCCPLL(1)MGTAVTTTX(1)MGTAVTTRX(1)MGTAVCC(1)MGTAVTTRXC(1)Notes:
1.2.
Description
Analog supply voltage for the GTP_DUAL shared PLL relative to GNDAnalog supply voltage for the GTP_DUAL transmitters relative to GNDAnalog supply voltage for the GTP_DUAL receivers relative to GNDAnalog supply voltage for the GTP_DUAL common circuits relative to GNDAnalog supply voltage for the resistor calibration circuit of the GTP_DUAL column
Min1.141.141.140.951.14
Max1.261.261.261.051.26
UnitsVVVVV
Each voltage listed requires the filter circuit described in Virtex-5 FPGA RocketIO GTP Transceiver User Guide.Voltages are specified for the temperature range of Tj=–40°C to +100°C.
Table 26:DC Characteristics Over Recommended Operating Conditions for GTP_DUAL Tiles(1)
SymbolIMGTAVTTTXIMGTAVCCPLLIMGTAVTTRXCIMGTAVTTRXIMGTAVCCMGTRREFNotes:
1.2.3.
Typical values are specified at nominal voltage, 25°C, with a 3.2Gb/s line rate.
ICC numbers are given per GTP_DUAL tile with both GTP transceivers operating with default settings.AC coupled TX/RX link.
Description
GTP_DUAL tile transmitter termination supply current(2)GTP_DUAL tile shared PLL supply current
GTP_DUAL tile resistor termination calibration supply currentGTP_DUAL tile receiver termination supply current(3)GTP_DUAL tile internal analog supply current
Precision reference resistor for internal calibration termination
MinTyp71360.10.156
Max90600.50.5110
UnitsmAmAmAmAmA?
49.9 ±1% tolerance
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 59:Output Delay Measurement Methodology (Cont’d)
Description
HSTL, Class IVHSTL, Class I, 1.8VHSTL, Class II, 1.8VHSTL, Class III, 1.8VHSTL, Class IV, 1.8V
SSTL (Stub Series Terminated Logic), Class I, 1.8VSSTL, Class II, 1.8VSSTL, Class I, 2.5VSSTL, Class II, 2.5V
LVDS (Low-Voltage Differential Signaling), 2.5VLVDSEXT (LVDS Extended Mode), 2.5VBLVDS (Bus LVDS), 2.5VLDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V
LVDCI/HSLVDCI
(Low-Voltage Digitally Controlled Impedance), 3.3VLVDCI/HSLVDCI, 2.5VLVDCI/HSLVDCI, 1.8VLVDCI/HSLVDCI, 1.5VHSTL, Class III & IV, with DCIHSTL, Class I & II, 1.8V, with DCIHSTL, Class III & IV, 1.8V, with DCI
HSTL_IVHSTL_I_18HSTL_II_18HSTL_III_18HSTL_IV_18SSTL18_ISSTL18_IISSTL2_ISSTL2_IILVDS_25LVDS_25BLVDS_25LDT_25LVPECL_25
LVDCI_33, HSLVDCI_33LVDCI_25, HSLVDCI_25LVDCI_18, HSLVDCI_18LVDCI_15, HSLVDCI_15HSTL_III_DCI, HSTL_IV_DCIHSTL_I_DCI_18, HSTL_II_DCI_18HSTL_III_DCI_18, HSTL_IV_DCI_18
SSTL2_I_DCI, SSTL2_II_DCIGTL_DCIGTLP_DCI
I/O StandardAttributeRREF (?)2550255025502550251001001001001001M1M1M1M5050505050505050
CREF(1)(pF)00000000000000000000000000
VMEAS(V)0.9VREFVREF1.11.1VREFVREFVREFVREF0(4)0(4)0(4)0(4)0(4)1.651.250.90.75VREF0.9VREF1.1VREFVREF0.81.0
VREF(V)1.50.90.91.81.80.90.91.251.251.21.200.6000000.751.50.91.80.91.251.21.5
HSTL (High-Speed Transceiver Logic), Class I & II, with DCIHSTL_I_DCI, HSTL_II_DCI
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCISSTL18_I_DCI, SSTL18_II_DCISSTL, Class I & II, 2.5V, with DCI
GTL (Gunning Transceiver Logic) with DCIGTL Plus with DCINotes:
1.2.3.4.
CREF is the capacitance of the probe, nominally 0pF.Per PCI specifications.Per PCI-X specifications.
The value given is the differential input voltage.
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 69:DSP48E Switching Characteristics (Cont’d)
Symbol
TDSPCCK_CEPP/TDSPCKC_CEPP
Description
CEP input to Pregister CLK
Speed Grade-2I0.630.01
-1I0.730.01
-1M0.730.01
Unitsns
Setup and Hold Times of the RST PinsTDSPCCK_{RSTAA, RSTBB}/TDSPCKC_{RSTAA, RSTBB}
TDSPCCK_RSTCC/ TDSPCKC_RSTCCTDSPCCK_RSTMM/ TDSPCKC_RSTMM DTSPCCK_RSTPP/TDSPCKC_RSTPP
{RSTA, RSTB} input to {A, B} register CLKRSTC input to Cregister CLKRSTM input to Mregister CLKRSTP input to Pregister CLK
0.28
0.260.210.210.290.210.630.01
0.330.310.260.280.360.260.730.01
0.330.310.260.280.360.260.730.01
nsnsnsns
Combinatorial Delays from Input Pins to Output PinsTDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M
{A, B} input to {P, CARRYOUT} output using multiplier
3.221.771.67
3.842.222.08
3.842.222.08
nsnsns
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM {A, B} input to {P, CARRYOUT} output not
using multiplierTDSPDO_{CP, CCRYOUT, CRYINP, CRYINCRYOUT}
{C, CARRYIN} input to {P, CARRYOUT} output
Combinatorial Delays from Input Pins to Cascading Output PinsTDSPDO_{AACOUT, BBCOUT}
TDSPDO_{APCOUT, ACRYCOUT,
AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_M
TDSPDO_{APCOUT, ACRYCOUT,
AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_NM
TDSPDO_{CPCOUT, CCRYCOUT, CMULTSIGNOUT, CRYINPCOUT,
CRYINCRYCOUT, CRYINMULTSIGNOUT}
{A, B} input to
{ACOUT, BCOUT} output
{A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier{A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier{C, CARRYIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output
1.123.22
1.313.84
1.313.84
nsns
1.922.422.42ns
1.822.282.28ns
Combinatorial Delays from Cascading Input Pins to All Output PinsTDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_M
TDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_NM
TDSPDO_{ACINACOUT, BCINBCOUT} TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT,
BCINCRYCOUT, BCINMULTSIGNOUT}_M TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT,
BCINCRYCOUT, BCINMULTSIGNOUT}_NM
{ACIN, BCIN} input to {P, CARRYOUT} output using multiplier
{ACIN, BCIN} input to {P, CARRYOUT} output not using multiplier
{ACIN, BCIN} input to {ACOUT, BCOUT} output
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output using multiplier
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output not using multiplier
3.221.771.123.22
3.842.221.313.84
3.842.221.313.84
nsnsnsns
1.922.422.42ns
TDSPDO_{PCINP, CRYCINP, MULTSIGNINP, {PCIN, CARRYCASCIN, MULTSIGNIN} input
to {P, CARRYOUT} outputPCINCRYOUT, CRYCINCRYOUT,
MULTSIGNINCRYOUT}
1.451.821.82ns
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011Product Specification
FPGA可编程逻辑器件芯片XC2S30-5FGG456C中文规格书 - 图文
