实验七、简易电子时钟设计
一、简易电子时钟设计实验程序:
module clock(clk,clr,minute_h,minute_l,second_h,second_l); input clk; input clr; output [3:0] minute_h; output [3:0] minute_l; output [3:0] second_h; output [3:0] second_l; reg [3:0] minute_h; reg [3:0] minute_l; reg [3:0] second_h; reg [3:0] second_l; reg second_l_flag; reg second_h_flag; reg minute_l_flag; reg minute_h_flag; reg clk1; //实验时选为2hz的时钟频率 always @(posedge clk or negedge clr) begin if(!clr) clk1 <= 1'b0; else clk1 <= ~clk1; end //秒钟的低位 always @(posedge clk1 or negedge clr) if(!clr) begin second_l <= 4'b0000; second_l_flag <= 1'b0; end else if(second_l==4'b1000) begin second_l <= second_l + second_l_flag <= 1'b1; end else if(second_l < 4'b1000)
//分钟的高位 //分钟的低位 //秒钟的高位 //秒钟的低位 //秒钟低位的进位标志//秒钟高位的进位标志//分钟低位的进位标志//分钟高位的进位标志1'b1; begin second_l <= second_l + 1'b1; second_l_flag <= 1'b0; end else begin second_l <= 4'b0000; second_l_flag <= 1'b0; end
//秒钟的高位 always @(negedge second_l_flag or negedge clr) if(!clr) begin second_h <= 4'b0000; second_h_flag <= 1'b0; end else if(second_h==4'b0100) begin second_h <= second_h + 1'b1; second_h_flag <= 1'b1; end else if(second_h < 4'b0100) begin second_h <= second_h + 1'b1; second_h_flag <= 1'b0; end else begin second_h <= 4'b0000; second_h_flag <= 1'b0; end //分钟的低位 always @(negedge second_h_flag or negedge clr) if(!clr) begin minute_l <= 4'b0000; minute_l_flag <= 1'b0; end else if(minute_l==4'b1000)
begin minute_l <= minute_l + 1'b1; minute_l_flag <= 1'b1; end else if(minute_l < 4'b1000) begin minute_l <= minute_l + 1'b1; minute_l_flag <= 1'b0; end else begin minute_l <= 4'b0000; minute_l_flag <= 1'b0; end //分钟的高位 always @(negedge minute_l_flag or negedge clr) if(!clr) begin minute_h <= 4'b0000; minute_h_flag <= 1'b0; end else if(minute_h==4'b0100) begin minute_h <= minute_h + 1'b1; minute_h_flag <= 1'b1; end else if(minute_h < 4'b0100) begin minute_h <= minute_h + 1'b1; minute_h_flag <= 1'b0; end else begin minute_h <= 4'b0000; minute_h_flag <= 1'b0; end endmodule
二、简易电子时钟设计测试程序: `timescale 10ns/1ns module clock_test;