Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
SPECIFICATIONS
VCC = 2.70 V to 5.5 V (ADM706P/ADM706R/ADM708R), VCC = 3.00 V to 5.5 V (ADM70xS), VCC = 3.15 V to 5.5 V (ADM70xT), TA = TMIN to TMAX unless otherwise noted. Table 1. Parameter POWER SUPPLY VCC Operating Voltage Range Supply Current LOGIC OUTPUT Reset Threshold (VRST) Min 1.0 100 150 2.55 2.85 3.00 160 160 2.63 2.93 3.08 20 200 200 200 RESET OUTPUT VOLTAGE (ADM706R/ADM708R/ ADM706S/ADM708S/ADM706T/ADM708T) VOH VOL VOH VOL VOL RESET OUTPUT VOLTAGE (ADM706P) VOH VOL VOH VOL RESET OUTPUT VOLTAGE (ADM708R/ADM708S/ADM708T) VOH VOL VOH VOL WATCHDOG INPUT (ADM706P/ADM706R/ ADM706S/ADM706T) Watchdog Timeout Period WDI Pulse Width WDI Input Threshold VIL VIH VIL VIH WDI Input Current Typ Max 5.5 200 350 2.70 3.00 3.15 280 280 Unit V μA μA V V V mV ms ms ms Test Conditions/Comments VCC < 3.6 V VCC < 5.5 V ADM706P/ADM706R/ADM708R ADM706S/ADM708S ADM706T/ADM708T ADM706P/ADM706R/ADM708R, VCC = 3 V ADM706S/ADM708S/ADM706T/ADM708T, VCC = 3.3 V VCC = 5.0 V Reset Threshold Hysteresis RESET PULSE WIDTH 0.8 × VCC 0.3 VCC ? 1.5 V 0.4 0.3 VCC ? 0.6 V 0.3 VCC ? 1.5 V 0.4 V V V V V V V V V VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA VCC = 1 V, ISINK = 100 μA VRST (max) < VCC < 3.6 V, ISOURCE = 215 μA VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA 0.8 × VCC 0.3 VCC ? 1.5 V 0.4 V V V V VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA VRST (max) < VCC < 3.6 V, ISINK = 500 μA 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA 4.5 V < VCC < 5.5 V, ISINK = 1.2 mA 1.00 100 50 1.60 2.25 sec ns ns ADM706P/ADM706R: VCC = 3 V; ADM706S/ADM706T: VCC = 3.3 V; VIL = 0.4 V, VIH = VCC × 0.8 V VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V VRST (max) < VCC < 3.6 V VRST (max) < VCC < 3.6 V VCC = 5.0 V VCC = 5.0 V WDI = 0 V or VCC 0.6 0.7 × VCC 0.8 3.5 ?1.0 +0.02 +1.0 V V V V μA Rev. E | Page of 16
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
MR1VCC2GND38Data Sheet
WDOMR1VCC2GND306435-003ADM706P7RESETFigure 3. ADM706P Figure 4. ADM706R/ADM706S/ADM706T
Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T Pin No. 1 Mnemonic MR Description Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds the input high when floating. Power Supply Input. Place a 0.1 μF decoupling capacitor between the VCC and GND pins. Ground. Ground reference for all signals (0 V). Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is less than 1.25 V, PFO goes low. If unused, PFI connects to GND. Power Fail Output. PFO is the output from the power fail comparator. It goes low when PFI is less than 1.25 V. Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the watchdog output, WDO, goes low. The timer resets with each transition at the WDI input. Either a high to low or a low to high transition clears the counter. The internal timer is also cleared whenever reset is asserted. Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being below the reset threshold or by a low signal on the MR input. RESET remains low whenever VCC is below the reset threshold. It remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is connected to MR. Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the inverse of RESET. Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes low during low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As soon as VCC goes above the reset threshold, WDO goes high immediately. 2 3 4 5 6 VCC GND PFI PFO WDI 7 (ADM706R/ADM706S/ ADM706T Only) RESET 7 (ADM706P Only) 8 RESET WDO Rev. E | Page of 16
06435-0046WDITOP VIEW(Not to Scale)5PFOPFI46WDITOP VIEW5PFOPFI4(Not to Scale)ADM706R/ADM706S/ADM706T87WDORESETData Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
MR1VCC2GND3NC = NO CONNECTFigure 5. ADM708R/ADM708S/ADM708T
Table 4. Pin Function Descriptions ADM708R/ADM708S/ADM708T Pin No. 1 Mnemonic MR Description Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds the input high when floating. Power Supply Input. Place a 0.1 μF decoupling capacitor between the VCC and GND pins. Ground. Ground reference for all signals (0 V). Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is less than 1.25 V, PFO goes low. If unused, PFI must connect to GND. Power Fail Output. PFO is the output from the power fail comparator. It goes low when PFI is less than 1.25 V. No Connect. Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being below the reset threshold or by a low signal on the MR input. RESET remains low whenever VCC is below the reset threshold. It remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is connected to MR. Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the inverse of RESET. 2 3 4 5 6 7 VCC GND PFI PFO NC RESET 8 RESET Rev. E | Page of 16
06435-0056NCTOP VIEW5PFOPFI4(Not to Scale)ADM708R/ADM708S/ADM708T87RESETRESETADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
Rev. E | Page of 16
Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
OUTLINE DIMENSIONS
0.400 (10.16)0.365 (9.27)0.355 (9.02)850.280 (7.11)10.250 (6.35)40.240 (6.10)0.325 (8.26)0.310 (7.87)0.100 (2.54)0.300 (7.62)BSC0.060 (1.52)0.195 (4.95)0.210 (5.33)MAXMAX0.130 (3.30)0.115 (2.92)0.150 (3.81)0.015(0.38)0.130 (3.30)MIN0.015 (0.38)GAUGE0.115 (2.92)SEATINGPLANE0.014 (0.36)PLANE0.010 (0.25)0.022 (0.56)0.018 (0.46)0.005 (0.13)0.430 (10.92)0.008 (0.20)0.014 (0.36)MINMAX0.070 (1.78)0.060 (1.52)0.045 (1.14)COMPLIANTTO JEDEC STANDARDS MS-001CONTROLLING DIMENSIONS(INREFERENCE ONLYPARENTHESES)ARE IN INCHES; MILLIMETER DIMENSIONSCORNER LEADS MAY BE CONFIGUREDANDARE ROUNDED-OFF INCH EQUIVALENTS FORARE NOTAPPROPRIATE FOR USE IN DESIGN.AS WHOLE OR HALF LEADS.Figure 24. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimension shown in inches and (millimeters)
5.00(0.1968)4.80(0.1890)4.00(0.1574)856.20(0.2441)3.80(0.1497)145.80(0.2284)1.27BSC(0.0500)1.75(0.0688)0.50(0.0196)0.25(0.0099)45°0.25(0.0098)1.35(0.0532)0.10(0.0040)8°0°COPLANARITY0.51(0.0201)0.10SEATING0.31(0.0122)0.25(0.0098)1.27(0.0500)PLANE0.17(0.0067)0.40(0.0157)COMPLIANTTOJEDECSTANDARDSMS-012-AACONTROLLINGA-(INDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS704REFERENCEPARENTHESES)ONLYANDAREAREROUNDED-OFFNOTAPPROPRIATEMILLIMETERFOREQUIVALENTSUSEINDESIGN.FOR210Figure 25. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. E | Page of 16
A-606070
MEMORY存储芯片ADM706TARZ-REEL中文规格书 - 图文
