Chapter5
Dynamic Reconfiguration Port (DRP)
Dynamic Reconfiguration of Functional Blocks
Background
In the Virtex-5 family of FPGAs, the configuration memory is used primarily to implement user logic, connectivity, and I/Os, but it is also used for other purposes. For example, it is used to specify a variety of static conditions in functional blocks, such as clock management tiles (CMTs).
Sometimes an application requires a change in these conditions in the functional blocks while the block is operational. This can be accomplished by partial dynamic
reconfiguration using the JTAG, ICAP, or SelectMAP ports. However, the dynamic
reconfiguration port that is an integral part of each functional block simplifies this process greatly. Such configuration ports exist in the CMTs.
Overview
This document describes the addressable, parallel write/read configuration memory that is implemented in each functional block that might require reconfiguration. This memory has the following attributes:???
It is directly accessible from the FPGA fabric. Configuration bits can be written toand/or read from depending on their function.
Each bit of memory is initialized with the value of the corresponding configurationmemory bit in the bitstream. Memory bits can also be changed later through the ICAP.The output of each memory bit drives the functional block logic, so the content of thismemory determines the configuration of the functional block.
The address space can include status (read-only) and function enables (write-only). Read-only and write-only operations can share the same address space. Figure5-1 shows how the configuration bits drive the logic in functional blocks directly in earlier FPGA families, and Figure5-2 shows how the reconfiguration logic changes the flow to read or write the configuration bits.
All configuration bits for this block Configuration Logic to Block LogicFunctional Block (DCM or MGT) UG191_c5_01_050406
Figure 5-1:Block Configuration Logic without Dynamic Interface
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 5:Dynamic Reconfiguration Port (DRP)
StandardReconfigurationPort (to Fabric)Logic Plane Block Status (Read-Only Ports) CONTROLLER Function Enables (Write-Only Ports) Reconfigurable Bits All configuration bits for this block Non-Reconfigurable BitsConfiguration Logic Functional Block (DCM or MGT) to Block Logicto Block LogicUG191_c5_02_050406Figure 5-2:Block Configuration Logic with Dynamic Interface
Figure5-3 is the same as Figure5-2, except the port between the Logic Plane and Functional Block is expanded to show the actual signal names and directions.
DCLK DEN DWE DADDR[m:0] DI[n:0] DO[n:0] DRDY StandardReconfigurationPort (to Fabric)Block Status (Read-Only Ports) CONTROLLER Function Enables (Write-Only Ports) Logic Plane Reconfigurable Bits All configuration bits for this block Non-Reconfigurable BitsConfiguration Logic Functional Block (DCM or MGT) UG191_c5_03_050406
to Block Logicto Block LogicFigure 5-3:Block Configuration Logic Expanded to Show Signal Names
FPGA Fabric Port Definition
Table5-1, page108, lists each signal on the FPGA Fabric port. The individual functional blocks can implement all or only a subset of these signals. The DCM chapter in the Virtex-5 User Guide shows the signals and functions implemented for the specific blocks. In general, the port is a synchronous parallel memory port, with separate read and write buses similar to the block RAM interface. Bus bits are numbered least-significant to most-significant, starting at 0. All signals are active High.
Synchronous timing for the port is provided by the DCLK input, and all the other input signals are registered in the functional block on the rising edge of DCLK. Input (write) data
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
Chapter 5:Dynamic Reconfiguration Port (DRP)
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
FPGA可编程逻辑器件芯片XC2V6000-6FF1517I中文规格书
