Chapter1
Introduction to the RocketIO GTX Transceiver
Overview
The RocketIO? GTX transceiver is a power-efficient transceiver for Virtex?-5 FPGAs. The GTX transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides the following features to support a wide variety of applications:???
Current Mode Logic (CML) serial drivers/buffers with configurable termination,voltage swing, and coupling.
Programmable TX pre-emphasis, RX equalization, and linear and decision feedbackequalization (DFE) for optimized signal integrity.
Line rates from 750Mb/s to 6.5Gb/s, with optional 5x digital oversampling requiredfor rates between 150Mb/s and 750Mb/s. The nominal operation range of the sharedPMA PLL is from 1.5GHz to 3.25GHz. These are nominal values, see DS202: Virtex-5FPGA Data Sheet for specifications.
Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channelbonding, and clock correction.
Fixed latency modes for minimized, deterministic datapath latency.
Beacon signaling for PCI Express? designs and Out-of-Band signaling includingCOM signal support for SATA designs.
RX/TX Gearbox provides header insertion and extraction support for 64B/66B and64B/67B (Interlaken) protocols.Receiver eye scan:
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Vertical eye scan in the voltage domain for testing purposesHorizontal eye scan in the time domain for testing purposes
The first-time user is recommended to read High-Speed Serial I/O Made Simple [Ref1], which discusses high-speed serial transceiver technology and its applications.
Table1-1 lists some of the standard protocols designers can implement using the GTX transceiver. The Xilinx? CORE Generator? tool includes a Wizard to automatically configure GTX transceivers to support one of these protocols or perform custom configuration (see Chapter2, “RocketIO GTX Transceiver Wizard”).
The GTX_DUAL tile offers a data rate range and features that allow physical layer support for various protocols as illustrated in Table1-1.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Ports and Attributes
Table 1-3:GTX_DUAL Port Summary (Cont’d)Port
DirIn
DomainRXUSRCLK2
Description
DFE tap 2 weight value control for each transceiver (4-bit resolution plus 1-bit sign).
Section (Page)Decision Feedback Equalization (page167)
DFETAP20[4:0]DFETAP21[4:0]
DFETAP2MONITOR0[4:0]DFETAP2MONITOR1[4:0]DFETAP30[3:0]DFETAP31[3:0]
DFETAP3MONITOR0[3:0]DFETAP3MONITOR1[3:0]DFETAP40[3:0]DFETAP41[3:0]
DFETAP4MONITOR0[3:0]DFETAP4MONITOR1[3:0]
OutRXUSRCLK2
DFE tap 2 weight value monitor
Decision Feedback
for each transceiver (4-bit
Equalization (page167)
resolution plus 1-bit sign).DFE tap 3 weight value control for each transceiver (3-bit resolution plus 1-bit sign).
Decision Feedback Equalization (page167)
InRXUSRCLK2
OutRXUSRCLK2
DFE tap 3 weight value monitor
Decision Feedback
for each transceiver (3-bit
Equalization (page167)
resolution plus 1-bit sign).DFE tap 4 weight value control for each transceiver (3-bit resolution plus 1-bit sign).
Decision Feedback Equalization (page167)
InRXUSRCLK2
OutRXUSRCLK2
DFE tap 4 weight value monitor
Decision Feedback
for each transceiver (3-bit
Equalization (page167)
resolution plus 1-bit sign).Data bus for writing
configuration data from the FPGA logic to the GTX_DUAL tile.
Data bus for reading
configuration data from the GTX_DUAL tile to the FPGA logic.
Dynamic Reconfiguration Port (page117)
DI[15:0]InDCLK
DO[15:0]OutDCLK
Dynamic Reconfiguration Port (page117)
DRDYOutDCLK
Indicates the operation is complete for DRP write
operations and data is valid for DRP read operations.Indicates whether the DRP operation is a read or a write.Starts the full GTX_DUAL reset sequence.
Factory test pins. Do not change default value.
Dynamic Reconfiguration Port (page117)
Dynamic Reconfiguration Port (page117)Reset (page102)
DWEGTXRESETGTXTEST[13:0]
InInIn
DCLKAsyncAsync
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 1:Introduction to the RocketIO GTX Transceiver
Table 1-3:GTX_DUAL Port Summary (Cont’d)Port
Dir
Domain
Description
Section (Page)
INTDATAWIDTHInAsync
Shared PMA PLL (page87), FPGA TX Interface (page120),
Parallel In to Serial Out
Sets the internal datapath width (page149), Serial In to
Parallel Out (page183), for the GTX_DUAL tile.
PRBS Detection (page190),
0: 16-bit internal datapath
Configurable RX Elastic
width
Buffer and Phase Alignment
1: 20-bit internal datapath (page205), Configurable widthClock Correction (page212),
Configurable Channel Bonding (Lane Deskew) (page219), FPGA RX Interface (page236)Sets the loopback mode.
Loopback (page250)
LOOPBACK0[2:0]LOOPBACK1[2:0]PHYSTATUS0PHYSTATUS1
InAsync
OutAsync
Indicates completion of several
Receive Detect Support for
PHY functions, including power
PCI Express Operation
management state transitions
(page154)
and receiver detection.Indicates that the VCO rate is within acceptable tolerances of the desired rate.
Enables the PLL lock detector.Powers down the shared PMA PLL.
Resets the PRBS error counter.
Shared PMA PLL (page87)Shared PMA PLL (page87)Power Control (page110)PRBS Detection (page190)Shared PMA PLL (page87), Clocking (page98), FPGA TX Interface (page120), TX Buffering, Phase Alignment, and TX Skew Reduction (page143),
FPGA RX Interface (page236)
PLLLKDETPLLLKDETENPLLPOWERDOWNPRBSCNTRESET0PRBSCNTRESET1
OutInInIn
AsyncAsyncAsyncRXUSRCLK2
REFCLKOUTOutN/A
Provides access to the reference clock provided to the shared PMA PLL (CLKIN).
REFCLKPWRDNBRESETDONE0RESETDONE1
InAsync
Powers down the GTX reference
Power Control (page110)
clock circuit (active Low).
Indicates when the GTX
Reset (page102), RX Clock
transceiver has finished reset and
Data Recovery (page179)
is ready for use.
OutAsync
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 1:Introduction to the RocketIO GTX Transceiver
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Package Placement Information
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC2S200E-7FG676I中文规格书 - 图文
