MEMORY存储芯片MT29F8G16ADBDAH4-ITD中文规格书 - 图文

Electrical Specifications – IDD Specifications and Conditions

Within the following IDD measurement tables, the following definitions and conditionsare used, unless stated otherwise:????????????????

LOW: VIN ?? VIL(AC)max; HIGH: VIN ?? VIH(AC)min.Midlevel: Inputs are VREF = VDD/2.RON set to RZQ/7 (34?).RTT,nom set to RZQ/6 (40?).RTT(WR) set to RZQ/2 (120?).QOFF is enabled in MR1.

ODT is enabled in MR1 (RTT,nom) and MR2 (RTT(WR)).TDQS is disabled in MR1.

External DQ/DQS/DM load resistor is 25? to VDDQ/2.Burst lengths are BL8 fixed.AL equals 0 (except in IDD7).

IDD specifications are tested after the device is properly initialized.Input slew rate is specified by AC parametric test conditions.Optional ASR is disabled.

Read burst type uses nibble sequential (MR0[3] = 0).

Loop patterns must be executed at least once before current measurements begin.

Table 9: Timing Parameters Used for IDD Measurements – Clock Units

DDR3L-800IDDParametertCK (MIN) IDDDDR3L-1066-187E7-7-777272072027465986139187-1878-8-888282082027465986139187DDR3L-1333-15E9-9-99933249203045741071742341.5101034241020304574107174234101038281024325688-15DDR3L-1600-125E1.25111139281124325688128208280-125DDR3L-1866-1071.071313453213263356103150243328DDR3L-2133-0930.9381414503614273867118172279375nsCKCKCKCKCKCKCKCKCKCKCKCKCK-25E5-5-52.55DD-256-6-66621156162044446410414010-10-1010-10-1011-11-1113-13-1314-14-14Unit1.875CL IDDtRCD (MIN) ItRC (MIN) I5201551620444464104140DDDDtRAS (MIN) ItRP (MIN)tFAWx4, x8x16x4, x8x161Gb2Gb4Gb8GbtRRDIDDtRFC12820828009005aef85af8fa8

4Gb_DDR3L.pdf - Rev. R 09/18 EN

Electrical Characteristics and AC Operating Conditions

Table 58: Electrical Characteristics and AC Operating Conditions

Notes 1–8 apply to the entire tableDDR3L-800ParameterClock period average:DLL disable modeTC ? 85°CTC = >85°C to 95°CSymboltCK09005aef85af8fa84Gb_DDR3L.pdf - Rev. R 09/18 ENDDR3L-1066Min880.470.47–90–80Max780039000.530.539080DDR3L-1333Min880.470.47–80–70Max780039000.530.538070DDR3L-1600Min880.470.47–70–60Max780039000.530.537060UnitnsnsnsCKCKpspspstCKMin880.470.47–100–90Max780039000.530.5310090Notes9, 424210, 111212Clock Timing(DLL_DIS)tCK (AVG)tCH (AVG)tCL (AVG)tJITpertJITper,lcktCK (ABS)tCH (ABS)tCL (ABS)tJITcctJITcc,lcktERR2pertERR3pertERR4pertERR5pertERR6pertERR7pertERR8pertERR9pertERR10pertERR11pertERR12pertERRnperClock period average: DLL enable modeHigh pulse width averageLow pulse width averageClock period jitterClock absolute periodClock absolute high pulse widthClock absolute low pulse widthCycle-to-cycle jitterDLL lockedDLL lockingCumulative error across2 cycles3 cycles4 cycles5 cycles6 cycles7 cycles8 cycles9 cycles10 cycles11 cycles12 cyclesn = 13, 14 . . . 49, 50cyclesDLL lockedDLL lockingSee Speed Bin Tables for tCK range allowed4Gb: x4, x8, x16 DDR3L SDRAMElectrical Characteristics and AC Operating Conditions1313MIN = tCK (AVG) MIN + tJITper MIN; MAX = tCK (AVG) MAX + tJITperMAX0.430.43200180–147–175–194–209–222–232–241–249–257–263–269147175194209222232241249257263269–132–157–175–188–200–209–217–224–231–237–242––0.430.43180160132157175188200209217224231237242–118–140–155–168–177–186–193–200–205–210–215––0.430.43160140118140155168177186193200205210215–103–122–136–147–155–163–169–175–180–184–188––0.430.43140120103122136147155163169175180184188––14151616171717171717171717171717(AVG)tCK(AVG)pspspspspspspspspspspspspspstERRnper MIN = (1 + 0.68ln[n]) × tJITper MINtERRnper MAX = (1 + 0.68ln[n]) × tJITper MAX09005aef85af8fa84Gb_DDR3L.pdf - Rev. R 09/18 ENTable 58: Electrical Characteristics and AC Operating Conditions (Continued)

Notes 1–8 apply to the entire tableDDR3L-800ParameterData setup time toDQS, DQS#Data setup time toDQS, DQS#Data hold time fromDQS, DQS#Base (specification)VREF @ 1 V/nsBase (specification)VREF @ 1 V/nsBase (specification)VREF @ 1 V/nstDHtDSDDR3L-1066Min4020090250110200490–0.38–600––0.250.450.450.20.20.90.3–30010.380.38Max–––––––150–3003000.250.550.55––––30010––DDR3L-1333Min––4518075165400–0.38–500––0.250.450.450.20.20.90.3–25510.400.40Max–––––––125–2502500.250.550.55––––25510––DDR3L-1600Min––2516055145360–0.38–450––0.270.450.450.180.180.90.3–22510.400.40Max–––––––100–2252250.270.550.55––––22510––UnitpspspspspspspspstCKSymboltDSMin90250140275160250600–0.38–800––0.250.450.450.20.20.90.3–40010.380.38Max–––––––200–4004000.250.550.55––––40010––Notes18, 19, 4419, 2018, 19, 4419, 2018, 19DQ Input Timing(AC160)(AC135)4Gb: x4, x8, x16 DDR3L SDRAMElectrical Characteristics and AC Operating Conditions(DC90)tDIPW19, 2041Minimum data pulse widthDQS, DQS# to DQ skew, per accessDQ output hold time from DQS, DQS#DQ Low-Z time from CK, CK#DQ High-Z time from CK, CK#DQS, DQS# rising to CK, CK# risingDQS, DQS# differential input low pulse widthDQS, DQS# differential input high pulsewidthDQS, DQS# falling setup to CK, CK# risingDQS, DQS# falling hold from CK, CK# risingDQS, DQS# differential WRITE preambleDQS, DQS# differential WRITE postambleDQS, DQS# rising to/from rising CK, CK#DQS, DQS# rising to/from rising CK, CK#when DLL is disabledDQS, DQS# differential output high timeDQS, DQS# differential output low timeDQ Output TimingtDQSQtQHtLZDQtHZDQ2122, 2322, 2325(AVG)pspsCKCKCKCKCKCKCKpsnsCKCK232621212525DQ Strobe Input TimingtDQSStDQSLtDQSHtDSStDSHtWPREtWPSTDQ Strobe Output TimingtDQSCKtDQSCK(DLL_DIS)tQSHtQSL4Gb: x4, x8, x16 DDR3L SDRAM

Command and Address Setup, Hold, and Derating

Command and Address Setup, Hold, and Derating

The total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS (base) and tIH (base) values (see Table 60; values come from the Electrical

Characteristics and AC Operating Conditions table) to the ?tIS and ?tIH derating values(see Table 61 (page 104), Table 62 (page 104) or Table 63 (page 104)) respectively. Ex-ample: tIS (total setup time) = tIS (base) + ?tIS. For a valid transition, the input signalhas to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 64 (page 105)).Although the total setup time for slow slew rates might be negative (for example, a validinput signal will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transi-tion), a valid input signal is still required to complete the transition and to reach

VIH(AC)/VIL(AC) (see Figure 15 (page 53) for input signal requirements). For slew rates thatfall between the values listed in Table 61 (page 104) and Table 63 (page 104), the derat-ing values may be obtained by linear interpolation.

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between thelast crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew ratefor a falling signal is defined as the slew rate between the last crossing of VREF(DC) andthe first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slewrate line between the shaded VREF(DC)-to-AC region, use the nominal slew rate for derat-ing value (see Figure 34 (page 106)). If the actual signal is later than the nominal slewrate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a tangentline to the actual signal from the AC level to the DC level is used for derating value (see Figure 36 (page 108)).

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between thelast crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew ratefor a falling signal is defined as the slew rate between the last crossing of VIH(DC)min andthe first crossing of VREF(DC). If the actual signal is always later than the nominal slewrate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derat-ing value (see Figure 35 (page 107)). If the actual signal is earlier than the nominal slewrate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangentline to the actual signal from the DC level to the VREF(DC) level is used for derating value(see Figure 37 (page 109)).

Table 60: DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based

SymboltIS(base, AC160)tIS(base, AC135)tIS(base, AC125)tIH(base, DC90)800215365–2851066140290–210133380205–150160060185–1301866–651501102133–60135105UnitpspspspsReferenceVIH(AC)/VIL(AC)VIH(AC)/VIL(AC)VIH(AC)/VIL(AC)VIH(DC)/VIL(DC)09005aef85af8fa8

4Gb_DDR3L.pdf - Rev. R 09/18 EN

4Gb: x4, x8, x16 DDR3L SDRAM

Commands – Truth Tables

09005aef85af8fa8

4Gb_DDR3L.pdf - Rev. R 09/18 EN