Output Delay Measurements
Output delays are measured using a Tektronix P6245TDS500/600 probe (<1pF) across approximately 4 inchesof FR4 microstrip trace. Standard termination was used forall testing. The propagation delay of the 4 inch trace is char-acterized separately and subtracted from the final measure-ment, and is therefore not included in the generalized testsetup shown in Figure4.
Measurements and test conditions are reflected in the IBISmodels except where the IBIS format precludes it. Parame-ters VREF, RREF, CREF, and VMEAS fully describe the testconditions for each I/O standard. The most accurate predic-tion of propagation delay in any given application can beobtained through IBIS simulation, using the followingmethod:
1.Simulate the output driver of choice into the generalized
test setup, using values from Table31.2.Record the time to VMEAS.
3.Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or capacitance value to represent the load.4.Record the time to VMEAS.
5.Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual worst-case
propagation delay (clock-to-input) of the PCB trace.
VREFFPGA OutputRREF(voltage level when taking delay measurement)VMEASCREF (probe capacitance)DS302_05_031708Description
LVTTL (Low-Voltage Transistor-Transistor Logic)LVCMOS (Low-Voltage CMOS), 3.3VLVCMOS, 2.5VLVCMOS, 1.8VLVCMOS, 1.5VLVCMOS, 1.2V
PCI (Peripheral Component Interface), 33 MHz, 3.3VPCI, 66 MHz, 3.3VPCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)GTL Plus
HSTL (High-Speed Transceiver Logic), Class IHSTL, Class IIHSTL, Class IIIHSTL, Class IVHSTL, Class I, 1.8VHSTL, Class II, 1.8VHSTL, Class III, 1.8V
DS302 (v3.7) September 9, 2009Product Specification
I/O StandardAttribute
LVTTL (all)LVCMOS33LVCMOS25LVCMOS18LVCMOS15LVCMOS12
PCI33_3 (rising edge)PCI33_3 (falling edge)PCI66_3 (rising edge)PCI66_3 (falling edge)PCIX (rising edge)PCIX (falling edgeGTLGTLPHSTL_IHSTL_IIHSTL_IIIHSTL_IVHSTL_I_18HSTL_II_18HSTL_III_18
RREF CREF(1)
(pF)(Ω)
1M1M1M1M1M1M2525252525252525502550255025
00000010(2)10(2)10(2)10(2)10(3)10(3)00000000
VMEAS
(V)
1.41.651.250.90.750.750.942.030.942.030.942.030.81.0VREFVREF0.90.9VREFVREF
VREF(V)
00000003.303.33.31.21.50.750.751.51.50.90.9
5001.11.8
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
CLB Switching Characteristics
Table 37: CLB Switching Characteristics
Speed Grade-12
Symbol
Combinatorial DelaysTILOTIF5TIF5XTIF6YTINAFXTINBFXTBXXTBYYTBXCYTBYCYTBYPTOPCYFTOPCYG
Sequential DelaysTCKOTCKLOTDICK/TCKDITCECK/TCKCETFXCK/TCKFXTSRCK/TCKSRTCINCK/TCKCINSet/ResetTRPWTRQFTOG
Minimum Pulse Width, SR/BY inputsDelay from SR/BY inputs to XQ/YQ outputs (asynchronous)
Toggle Frequency (MHz) (for export control)
0.541.051181
0.531.031205
0.591.151205(4)
0.701.351028
ns, Minns, MaxMHz
FF Clock CLK to XQ/YQ outputsLatch Clock CLK to XQ/YQ outputs
0.280.37
0.280.36
0.310.41
0.360.48
ns, Maxns, Max
4-input function: F/G inputs to X/Y outputs5-input function: F/G inputs to F5 output5-input function: F/G inputs to X outputFXINA or FXINB inputs to YMUX outputFXINA input to FX output via MUXFXFXINB input to FX output via MUXFXBX input to XMUX outputBY input to YMUX output
BX input to COUT output – Getting into carry chain(3)BY input to COUT output – Getting into carry chain(3)CIN input to COUT output – Carry chain delay(3)
F input to COUT output – Getting out from carry chain(3)G input to COUT output – Getting out from carry chain(3)
0.150.360.440.300.210.210.590.430.600.490.070.450.44
0.150.350.430.300.210.200.580.430.590.480.070.440.43
0.170.400.490.340.230.230.650.480.660.540.080.500.48
0.200.460.570.390.270.260.760.560.780.630.090.580.57
ns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Max
-11-10
Units
DescriptionXC4VFX(2)
XC4VLX/SXALL DEVICES
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
BX/BY inputsCE input
FXINA/FXINB inputsSR/BY inputs (synchronous)
CIN Data Inputs (DI) – Getting out from carry chain(3)
0.36–0.090.58–0.160.42–0.141.04–0.740.52–0.23
0.36–0.090.57–0.160.41–0.141.02–0.730.51–0.23
0.40–0.090.64–0.160.46–0.141.15–0.730.57–0.23
0.47–0.090.75–0.160.54–0.141.35–0.730.67–0.23
ns, Minns, Minns, Minns, Minns, Min
Notes:
1.A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2.The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent 4VLX/SX
-12 column.
3.These items are of interest for Carry Chain applications.4.XC4VFX -11 devices are 1181MHz.
DS302 (v3.7) September 9, 2009Product Specification
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 38: CLB Distributed RAM Switching Characteristics
Speed Grade-12
Symbol
Sequential DelaysTSHCKOTSHCKOF5
Clock CLK to X outputs (WE active)(3)Clock CLK to F5 output (WE active)
1.611.531.26–0.900.88–0.371.10–0.480.530.550.76
1.581.501.23–0.880.86–0.371.08–0.470.520.540.74
1.771.691.46–0.880.97–0.341.21–0.470.590.600.84
2.081.981.80–0.881.13–0.291.42–0.470.690.700.98
ns, Maxns, Max
-11-10
Units
DescriptionXC4VFX(2)
XC4VLX/SXALL DEVICES
Setup and Hold Times Before/After Clock CLKTDS/TDHTAS/TAHTWS/TWHClock CLKTWPHTWPLTWC
Minimum Pulse Width, HighMinimum Pulse Width, Low
Minimum clock period to meet address write cycle time
ns, Minns, Minns, Min
BX/BY data inputs (DI)F/G address inputsWE input (SR)
ns, Minns, Minns, Min
DS302 (v3.7) September 9, 2009Product Specification
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 45: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode (Continued)
Speed Grade
Symbol
CLKOUT_FREQ_FX_HF_MS_MINCLKOUT_FREQ_FX_HF_MS_MAXInput Clocks (High Frequency Mode)CLKIN_FREQ_DLL_HF_MS_MIN(6)CLKIN_FREQ_DLL_HF_MS_MAXCLKIN_FREQ_FX_HF_MS_MINCLKIN_FREQ_FX_HF_MS_MAX(6)PSCLK_FREQ_HF_MS_MINPSCLK_FREQ_HF_MS_MAX
CLKIN (using DLL outputs only)(1,3,4,5)CLKIN (using DFS outputs)(2,3,4)PSCLK
150500503501500
150450503151450
150400503001400
MHzMHzMHzMHzKHzMHz
Description
CLKFX, CLKFX180
-12
210350
-11
210315
-10
210300
Units
MHzMHz
DS302 (v3.7) September 9, 2009Product Specification
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 47: Input Clock Tolerances
Symbol
Duty Cycle Input Tolerance (in%)CLKIN_PSCLK_PULSE_RANGE_1CLKIN_PSCLK_PULSE_RANGE_1_50CLKIN_PSCLK_PULSE_RANGE_50_100CLKIN_PSCLK_PULSE_RANGE_100_200CLKIN_PSCLK_PULSE_RANGE_200_400CLKIN_PSCLK_PULSE_RANGE_400
PSCLK and CLKINPSCLK only
< 1MHz1 – 50MHz(1)50 – 100MHz(1)100 – 200MHz(1)200 – 400MHz(1)
>400MHz
25-7525-7530-7040-6045-5545-55
%%%%%%
Description
Frequency Range
ValueUnits
DS302 (v3.7) September 9, 2009Product Specification
FPGA可编程逻辑器件芯片XC4VLX40-11FF1148I中文规格书 - 图文
