STM32F429xx
ARM Cortex-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT
Data brief
Features
? Core: ARM 32-bit Cortex?-M4 CPU with FPU, Adaptive real-time accelerator (ART
Accelerator?) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions ? Memories
– Up to 2 MB of Flash memory organized into two banks allowing read-while-write
– Up to 256+4 KB of SRAM including 64-KB of CCM (core coupled memory) data RAM – Flexible external memory controller with up to 32-bit data bus: SRAM,PSRAM,SDRAM, Compact Flash/NOR/NAND memories ? LCD parallel interface, 8080/6800 modes ? LCD-TFT controller up to VGA resolution with dedicated Chrom-ART Accelerator? for enhanced graphic content creation (DMA2D) ? Clock, reset and supply management
– 1.8 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1% accuracy)
– 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration ? Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM ? 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode ? 2×12-bit D/A converters
? General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
? Up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input ? Debug mode
– SWD & JTAG interfaces
LQFP100 (14 × 14 mm)LQFP144 (20 × 20 mm) UFBGA176 (10 × 10 mm)LQFP176 (24 × 24 mm) TFBGA216 (13 x 13 mm)WLCSP143LQFP208 (28 x 28 mm)
– Cortex-M4 Embedded Trace Macrocell? ? Up to 168 I/O ports with interrupt capability – Up to 164 fast I/Os up to 84 MHz – Up to 166 5 V-tolerant I/Os ? Up to 21 communication interfaces
– Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/4 UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control)
– Up to 6 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S for audio class accuracy via internal audio PLL or external clock – 1 x SAI (serial audio interface)
– 2 × CAN (2.0B Active) and SDIO interface ? Advanced connectivity
– USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII ? 8- to 14-bit parallel camera interface up to 54 MBs/s
? True random number generator ? CRC calculation unit ? 96-bit unique ID
? RTC: subsecond accuracy, hardware calendar
Table 1. Device summary
Reference Part number
STM32F429VG, STM32F429ZG, STM32F429IG,STM32F429VI, STM32F429ZI, STM32F429II,STM32F429BG, STM32F429BI, STM32F429NI,STM32F429NG
STM32F429xx
May 2013
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For further information contact your local STMicroelectronics sales office.
1
Contents STM32F429xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Full compatibility throughout the family
. . . . . . . . . . . . . . . . . . . . . . . . . .
7 8
.11
2
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17
ARM? Cortex?-M4 with FPU and embedded Flash and SRAM . . . . . . . Adaptive real-time memory accelerator (ART Accelerator?)
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Flash memory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . .
14
14 14 15 15 15 15 16 17 17 18 18 18 18 19 19 19
19 20
. . . . . . . . . 14
CRC (cyclic redundancy check) calculation unit
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA controller (DMA)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chrom-ART Accelerator? (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power supply schemes Power supply supervisor
3.17.1 3.17.2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.18 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.18.1 3.18.2 3.18.3
Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . .
21
21 22 25
3.19 3.20 3.21
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Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3.22
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.22.1 3.22.2 3.22.3 3.22.4 3.22.5 3.22.6
Advanced-control timers (TIM1, TIM8)
. . . . . . . . . . . . . . . . . . . . . . . . .
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Independent watchdog
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
28 29 29 29 29 30
3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 3.37 3.38 3.39 3.40 3.41 3.42
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal synchronous/asynchronous receiver transmitters (USART) Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital-to-analog converter (DAC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30 . . 30 31 31 32 32 32 32 33 33 34 34 35 35 35 35 36 36 36 36
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Trace Macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 6.2
Package mechanical data Thermal characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38 76 81
81 94
5
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Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 96
96 98 99
Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1 A.2 A.3
USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . . USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . . Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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STM32F429xx List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F429xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F429xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F429xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F429xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . . WLCSP143, 0.4 mm pitch wafe level chip scale package mechanical data. . . . . . . . . . . . LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TFBGA216 - ultra thin fine pitch ball grid array 13 × 13 × 0.8mm
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F429xx
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36.
Compatible board design STM32F10xx/STM32F2xx/STM32F4xx
for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx
for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compatible board design between STM32F2xx and STM32F4xx
for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F429xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F429xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . STM32F42x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F42x WLCSP143 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F42x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F42x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F42x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F42x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F42x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . LQPF100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP143, 0.4 mm pitch wafe level chip scale package outline . . . . . . . . . . . . . . . . . . . LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . LQFP208 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TFBGA216 - ultra thin fine pitch ball grid array 13 × 13 × 0.8mm,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB controller configured as peripheral-only and used
in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . . USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . . USB controller configured as peripheral, host, or dual-mode
and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F429xx Introduction
1
Introduction
This databrief provides the description of the STM32F429xx line of microcontrollers. For more details on the whole STMicroelectronics STM32? family, please refer to Section 2.1: Full compatibility throughout the family.
The STM32F429xx databrief should be read in conjunction with the STM32F4xx reference manual.
For information on the Cortex?-M4 core, please refer to the Cortex?-M4 programming manual (PM0214), available from the web.
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Description STM32F429xx
2
Description
The STM32F429XX devices is based on the high-performance ARM? Cortex?-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision data- processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
The STM32F429xx devices incorporates high-speed embedded memories (Flash memory up to 2 Mbyte, up to 256 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces. ? ?
Up to three I2Cs
Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.
Four USARTs plus four UARTs
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), Two CANs
One SAI serial audio interface An SDIO/MMC interface Ethernet and the camera interface LCD-TFT display controller DMA2D controller.
? ? ? ? ? ? ? ?
Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a camera interface for CMOS sensors. Refer to Table 2: STM32F429xx features and peripheral counts for the list of peripherals available on each part number.
The STM32F429xx devices operates in the –40 to +105 °C temperature range from a 1.8 to 3.6 V power supply.
The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range with the use of an external power supply supervisor (refer to
Section 3.17.2: Internal reset OFF). A comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F429xx devices offers devices in 7 packages ranging from 100 pins to 216 pins. The set of included peripherals changes with the device chosen.
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9/102These features make the STM32F429xx microcontrollers suitable for a wide range of applications: ? Motor drive and application control ? Medical equipment
? Industrial applications: PLC, inverters, circuit breakers ? Printers, and scanners
? Alarm systems, video intercom, and HVAC ?
Home audio appliances
Figure 4 and Figure 4 show the general block diagram of the device family.
Table 2. STM32F429xx features and peripheral countsPeripherals STM32F429Vx STM32F429Zx STM32F429Ix STM32F429Bx STM32F429Nx Flash memory in Kbytes 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 DocID023140Rev2SRAM in Kbytes System 256(112+16+64+64) Backup 4 FMC memory controller Yes(1) Ethernet Yes General-purpose 10 Timers Advanced-control 2 Basic 2 Random number generator Yes SPI / I 2S 6/2 (full duplex)(2) I 2C 3 Communication USART/UART 4/4 USB OTG FS Yes interfaces USB OTG HS Yes CAN 2 SAI 1 SDIO Yes Description STM32F429xx
Table 2. STM32F429xx features and peripheral counts (continued)
Peripherals STM32F429Vx STM32F429Zx STM32F429Ix STM32F429Bx STM32F429Nx Camera interface Yes LCD-TFT Yes Chrom-ART Accelerator? (DMA2D) Yes GPIOs 12-bit ADC 82 114 140 168 3 Number of channels 16 24 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 180 MHz DocID023140Rev2Operating voltage 1.8 to 3.6 V(3) Operating temperatures Ambient temperatures: –40 to +85 °C /–40 to +105 °C Junction temperature: –40 to + 125 °C Packages LQFP100 WLCSP143 UFBGA176 LQFP144 LQFP176 LQFP208 TFBGA216 1. For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.available Bank2 in this can package. only support
a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply
supervisor (refer to Section 3.17.2: Internal reset OFF).
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STM32F429xx Description
2.1
Full compatibility throughout the family
The STM32F429xx devices are part of the STM32F4 family. They are fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle.
The STM32F429xx devices maintain a close compatibility with the whole STM32F10xx family. All functional pins are pin-to-pin compatible. The STM32F429xx, however, are not drop-in replacements for the STM32F10xx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xx to the STM32F42x family remains simple as only a few pins are impacted. Figure 1, Figure 2, and Figure 3, give compatible board designs between the STM32F4xx, STM32F2xx, and STM32F10xx families.
Figure 1. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx
for LQFP100 package
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Description STM32F429xx
Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx
for LQFP144 package
108
109
VSS
106
73 72 71
VSS
VSS
Signal from external power
supply supervisor
143 (PDR_ON)144
30
31
3637
1
0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration
VSS
VDD VSS
Two 0 Ω resistors connected to: - VSS for the STM32F10xx - VSS, VDD or NC for the STM32F2xx
VDD
VSS
VSS for STM32F10xx VDD for STM32F4xx
- VDD or signal from external power supply supervisor for the STM32F4xx
Figure 3. Compatible board design between STM32F2xx and STM32F4xx
for LQFP176 package ai18487d
133 132 89 48
- GND for STM32F2xx - BYPASS_REG for STM32F4xx 88 Signal from external power supply supervisor 176 171 (PDR_ON)1 4544 VDDVSS Two 0 Ω resistors connected to: - VSS, VDD or NC for the STM32F2xx - VDD or signal from external power supply supervisor for the STM32F4xx MS31835V1
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STM32F429xx Description
Figure 4. STM32F429xx block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
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Functional overview STM32F429xx
3
Functional overview
ARM? Cortex?-M4 with FPU and embedded Flash and SRAM
The ARM Cortex-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F42x family is compatible with all ARM tools and software. Figure 4 shows the general block diagram of the STM32F42x family.
3.1
Note: Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core.
3.2 Adaptive real-time memory accelerator (ART Accelerator?)
The ART Accelerator? is a memory accelerator which is optimized for STM32 industry- standard ARM? Cortex?-M4 with FPU processors. It balances the inherent performance advantage of the ARM Cortex-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 225 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 180 MHz.
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real- time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.
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STM32F429IGT6数据手册 - 引脚图 - 参数
