Chapter 7:Package Information
Package Outlines
Figure7–3.100-Pin Micro FineLine BGA Package Outline
TOP VIEWD11109BOTTOM VIEWPin A1Corner 87654321ABPin A1 IDCDeEFGHJKLEbA3A1A2Ae100-Pin FineLine Ball-Grid Array (FBGA)
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All dimensions and tolerances conform to ASME Y14.5 – 1994Controlling dimension is in millimeters
Pin A1 may be indicated by an ID dot, or a special feature, in its proximity onpackage surface
Package InformationDescriptionOrdering Code ReferencePackage AcronymSubstrate MaterialFFBGABTPackage Outline Dimension TableSpecificationSymbolMin.AA1—0.25MillimetersNom.——Max.1.55—MAX II Device Handbook
Chapter 8:Using MAX II Devices in Multi-Voltage SystemsMultiVolt Core and I/O Operation
MultiVolt Core and I/O Operation
MAX II devices include MultiVolt core I/O operation capability, allowing the core and I/O blocks of the device to be powered-up with separate supply voltages. The
VCCINT pins supply power to the device core and the VCCIO pins supply power to the device I/O buffers. The VCCINT pins can be powered-up with 1.8V for MAX IIG and MAX IIZ devices or 2.5/3.3V for MAX II devices. All the VCCIO pins for a given I/O bank that have MultiVolt capability should be supplied from the same voltage level (for example, 5.0, 3.3, 2.5, 1.8, or 1.5 V). See Figure8–2.
Figure8–2.Implementing a Multiple-Voltage System with a MAX II Device (Note1), (2), (3), (4)
1.8 V/2.5 V/3.3 VPower SupplyVCCINT5.0-VDeviceVCCIOMAX IIDeviceVCCIO3.3-VDeviceVCCIO2.5-VDeviceNotes to Figure8–2:
(1)For MAX IIG and MAX IIZ devices, VCCINT pins will only accept a 1.8-V power supply.(2)For MAX II devices, VCCINT pins will only accept a 2.5-V or 3.3-V power supply.
(3)MAX II devices can drive a 5.0-V TTL input when VCCIO = 3.3 V. To drive a 5.0-V CMOS, an open-drain setting with
internal I/O clamp diode and external resistor are required.
(4)MAX II devices can be 5.0-V tolerant with the use of an external resistor and the internal I/O clamp diode on EPM1270
and EPM2210 devices.
5.0-V Device Compatibility
A MAX II device can drive a 5.0-V TTL device by connecting the VCCIO pins of the MAX II device to 3.3 V. This is possible because the output high voltage (VOH) of a 3.3-V interface meets the minimum high-level voltage of 2.4 V of a 5.0-V TTL device. A MAX II device may not correctly interoperate with a 5.0-V CMOS device if the output of the MAX II device is connected directly to the input of the 5.0-V CMOS device. If the MAX II device‘s VOUT is greater than VCCIO, the PMOS pull-up transistor still conducts if the pin is driving high, preventing an external pull-up resistor from pulling the signal to 5.0V. To make MAX II device outputs compatible with 5.0-V CMOS devices, configure the output pins as open-drain pins with the I/O clamp diode enabled, and use an external pull-up resistor. See Figure8–3.
MAX II Device Handbook
Section III.User Flash Memory
MAX II Device Handbook
FPGA可编程逻辑器件芯片EP3C40U484I7N中文规格书
