drivers must be installed on the host PC prior to establishing communications with the VC707 board.
The USB Connector Pin Assignments and Signal Definitions between J17 and U44 are listed in Table1-19.
Table 1-19:
USB Connector J17 Pin Assignments and Signal Definitions
Net Name
Description
CP2103GM (U44)Pin7843229
NameREGINVBUSD–D+GND1CNR_GND
USB Connector (J17)Pin1234
NameVBUSD_ND_PGND
USB_UART_VBUSUSB_D_NUSB_D_PUSB_UART_GND
+5V VBUS Powered
Bidirectional differential serial data (N-side)Bidirectional differential serial data (P-side)Signal ground
Table1-20 shows the USB connections between the FPGA and the UART.
Table 1-20:
FPGA to UART Connections
FPGA (U1)
PinAR34AT32AU36AU33
FunctionRTSCTSTXRX
DirectionOutputInputOutputInput
IOSTANDARDLVCMOS18LVCMOS18LVCMOS18LVCMOS18
Schematic Net
NameUSB_CTSUSB_RTSUSB_RXUSB_TX
CP2013 Device (U12)
Pin22232425
FunctionCTSRTSRXDTXD
DirectionInputOutputInputOutput
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers [Ref20].
HDMI Video Output
[Figure1-2, callout 18]
The VC707 board provides a High-Definition Multimedia Interface (HDMI?) video output using the Analog Devices ADV7511KSTZ-P HDMI transmitter (U48). The HDMI output is provided on a Molex 500254-1927 HDMI type-A connector (P2). The ADV7511 is wired to support 1080P 60Hz YCbCr and RGB video modes through 36-bit input data mapping.The VC707 board supports the following HDMI device interfaces:??????
36 data lines
Independent VSYNC, HSYNCSingle-ended input CLKInterrupt Out Pin to FPGAI2CSPDIF
VC707 Evaluation BoardUG885 (v1.8) February 20, 2024
Chapter 1:VC707 Evaluation Board Features
The VC707 board I2C bus topology is shown in Figure1-22.
X-Ref Target - Figure 1-22U1FPGABank 15(2.5V)U52PCA954812C 1-to-8Bus SwitchCH0 - USER_CLK_SDL/SCLCH1 - FMC1_HPC_IIC_SDA/SCLCH2 - FMC2_HPC_IIC_SDA/SCLCH3 - EEPROM_IIC_SDA/SCLCH4 - SFP_IIC_SDA/SCLCH5 - IIC_SDA/SCL_HDMICH6 - IIC_SDA/SCL_DDR3CH7 - SI5324_SDA/SCLUG855_C1_22_021012IIC_SDA/SCL_MAINFigure 1-22:
I2C Bus Topology
User applications that communicate with devices on one of the downstream I2C buses must first set up a path to the desired bus through the U52 bus switch at I2C address 0x74 (0b1110100). Table1-24 lists the address for each bus.Table 1-24:
I2C Bus Addresses
I2C Switch Position
NA01234567
I2C Address
0b11101000b10111010bXXXXX000bXXXXX000b10101000b10100000b0111001
0b1010000, 0b00110000b1101000
I2C Device
PCA9548Si570 ClockFMC1 HPCFMC2 HPCM24C08 EEPROMSFP ModuleADV7512 HDMIDDR3 SODIMMSi5324 Clock
Notes:
1.Use the PCA9458 (U52) at I2C address 0x74 (0b1110100) to setup the path to these buses.
Information about the PCA9548 is available on the TI Semiconductor website [Ref25].
Caution!The PCA9548 U52 RESET_B pin 24 is connected to the FPGA U1 bank 15 pin AY42
via level-shifter U70. The FPGA pin AY42 LVCMOS18 net IIC_MUX_RESET_B_LS must be driven High to enable I2C bus transactions with the devices connected to U52.
VC707 Evaluation BoardUG885 (v1.8) February 20, 2024
Chapter 1:VC707 Evaluation Board Features
VC707 Evaluation BoardUG885 (v1.8) February 20, 2024
Feature Descriptions
VITA 57.1 FMC1 HPC Connector (Partially Populated)
[Figure1-2, callout 30]
The VC707 board implements two instances of the FMC HPC VITA 57.1 specification connector. This section discusses the FMC1 HPC J35 connector.
Note:The FMC1 HPC J35 connector is a keyed connector oriented so that a plug-on card faces
away from the VC707 board.
The VITA 57.1 FMC standard calls for two connector densities: a high pin count (HPC) and a low pin count (LPC) implementation. A 400 pin 10x40 position connector form factor is used for both versions. The HPC version is fully populated with all 400 pins present. The LPC version is partially populated with 160 pins.
The 10x40 rows of an FMC HPC connector provides pins for up to:?????
160 single-ended or 80 differential user-defined signals10 GTX transceivers2 GTX clocks4 differential clocks
159 ground and 15 power connections
The VC707 board FMC1 HPC connector J35 implements a subset of the maximum signal and clock connectivity capabilities:???????
80 differential user-defined pairs34 LA pairs (LA00-LA33)24 HA pairs (HA00-HA23)22 HB pairs (HB00-HB21)8 GTX transceivers2 GTX clocks2 differential clocks
The FMC1 HPC signals are distributed across GTX Quads 118 and 119. Each Quad has the VCCO voltage connected to VADJ.
Note:The VC707 board VADJ voltage for the FMC1 HPC (J35) connector is determined by the
FMC VADJ power sequencing logic described in FMC_VADJ Voltage Control.
VITA 57.1 FMC2 HPC Connector (Partially Populated)
[Figure1-2, callout 31]
The VC707 board implements two instances of the FMC HPC VITA 57.1 specification connector. This section discusses the FMC2 HPC J37 connector.
Note:The FMC2 HPC J37 connector is a keyed connector oriented so that a plug-on card faces
away from the VC707 board.
The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin Count (LPC) implementation. A 400pin 10x40 position connector form factor is used for both versions. The HPC version is fully populated with all 400 pins present. The LPC version is partially populated with 160 pins.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2024
Chapter 1:VC707 Evaluation Board Features
VC707 Evaluation BoardUG885 (v1.8) February 20, 2024
FPGA可编程逻辑器件芯片XC2S30-5FGG256I中文规格书 - 图文
