DS099 (v3.1) June 27, 2013Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows:?
Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristicsof other families. Values are subject to change. Although speed grades with this designation are considered relativelystable and conservative, some under-reporting might still occur. Use as estimates, not for production.
Preliminary: Based on complete early silicon characterization. Devices and speed grades with this designation areintended to give a better indication of the expected performance of production silicon. The probability of under-reporteddelays is greatly reduced compared to Advance data. Use as estimates, not for production.
Production: These specifications are approved only after silicon has been characterized over numerous productionlots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes.Parameter values are considered stable with no future changes expected.
Production-quality systems must only use FPGA designs compiled with a Production status speed file. FPGA designsusing a less mature speed file designation should only be used during system prototyping or preproduction qualification.FPGA designs with speed files designated as Advance or Preliminary should not be used in a production-qualitysystem.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx ISE? software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates.
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. The following applies unless otherwise noted: The parameter values published in this module apply to all Spartan?-3 devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades. All parameters representing voltages are measured with respect to GND.
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Mask and Fab Revisions
Some specifications list different values for one or more mask or fab revisions, indicated by the device top marking (see Package Marking, page5). The revision differences involve the power ramp rates, differential DC specifications, and DCM characteristics. The most recent revision (mask rev E and GQ fab/geometry code) is errata-free with improved specifications than earlier revisions.
Mask rev E with fab rev GQ has been shipping since 2005 (see XCN05009) and has been 100% of Xilinx Spartan-3 device shipments since 2006. SCD 0974 was provided to ensure the receipt of the rev E silicon, but it is no longer needed. Parts ordered under the SCD appended “0974” to the standard part number. For example, “XC3S50-4VQ100C” became “XC3S50-4VQ100C0974”.
Table 28:Absolute Maximum Ratings
SymbolVCCINTVCCAUXVCCOVREFVIN
Description
Internal supply voltage relative to GNDAuxiliary supply voltage relative to GNDOutput driver supply voltage relative to GNDInput reference voltage relative to GNDVoltage applied to all User I/O pins and Dual-Purpose pins relative to GND(2,4)Voltage applied to all Dedicated pins relative to GND(3)
ConditionsMin–0.5–0.5–0.5–0.5
Max1.323.003.75VCCO+0.5
4.44.3VCCAUX + 0.5
UnitsVVVVVV
Driver in a
high-impedance state
CommercialIndustrialAll temp. ranges
–0.95–0.85–0.5
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 33VOUTPInternalLogicVOUTNPNDifferentialI/O Pair PinsVOUTNVOUTPGND levelVOH50%VODVOCMVOLVOCM= Output common mode voltage =VOUTP + VOUTN2VOD= Output differential voltage =VOUTP - VOUTNVOH= Output voltage indicating a High logic levelVOL= Output voltage indicating a Low logic levelDS099-3_02_091710Figure 33:Differential Output Voltages
Table 38:DC Characteristics of User I/Os Using Differential Signal Standards
Signal StandardLDT_25 (ULVDS_25) LVDS_25BLVDS_25(5)LVDSEXT_25LVPECL_25(5)RSDS_25(6)DIFF_HSTL_II_18DIFF_SSTL2_II
Notes:
Mask(3) Revision
AllAll‘E’AllAll‘E’AllAll‘E’AllAll
VOD
Min (mV)Typ (mV)Max (mV)430(4)100200250100300–100200––
600––350–––––––
670600500450600700-600500––
VOCM
Min (V)0.4950.801.0–0.801.0–0.801.0––
VOH
Max (V)0.7151.61.5–1.61.5-1.61.5––
VOLMax (V)0.501.551.40–1.551.351.0051.551.400.40VTT – 0.80
Typ (V)0.600––1.20–––––––
Min (V)0.710.851.10–0.851.151.350.851.10VCCO – 0.40VTT + 0.80
1.2.3.4.5.6.
The numbers in this table are based on the conditions set forth in Table32 and Table37.
Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins of thedifferential signal pair.
Mask revision E devices have tighter output ranges but can be used in any design that was in a previous revision. See Mask and FabRevisions, page58.
This value must be compatible with the receiver to which the FPGA’s output pair is connected.
Each LVPECL_25 or BLVDS_25 output-pair requires three external resistors for proper output operation as shown in Figure34. EachLVPECL_25 or BLVDS_25 input-pair uses a 100W termination resistor at the receiver.
Only one of the differential standards RSDS_25, LDT_25, LVDS_25, and LVDSEXT_25 may be used for outputs within a bank.Each differential standard input-pair requires an external 100Ω termination resistor.
X-Ref Target - Figure 34LVPECL70ΩLVPECLZ0=50Ω240ΩZ0=50Ω100ΩBLVDS165ΩBLVDSZ0=50Ω140ΩZ0=50Ω100Ω70Ω165Ωds099-3_08_112105Figure 34:External Termination Required for LVPECL and BLVDS Output and Input
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 45:Timing for the IOB Output Path
Speed Grade
Symbol
Clock-to-Output Times
TIOCKP
When reading from the Output LVCMOS25(2), 12mA output Flip-Flop (OFF), the time from the drive, Fast slew rateactive transition at the OTCLK input to data appearing at the Output pin
XC3S200XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
1.281.95
1.472.24
nsns
DescriptionConditionsDevice-5Max(3)
-4Max(3)
Units
Propagation Times
TIOOP
The time it takes for data to travel from LVCMOS25(2), 12mA output the IOB’s O input to the Output pindrive, Fast slew rate
XC3S200
XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
TIOOLP
The time it takes for data to travel from the O input through the OFF latch to the Output pin
XC3S200XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
LVCMOS25(2), 12mA output drive, Fast slew rate
1.281.94
1.462.23
nsns
1.281.95
1.472.24
nsns
Set/Reset Times
TIOSRP
Time from asserting the OFF’s SR input to setting/resetting data at the Output pin
XC3S200XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000All
2.102.77
2.413.18
nsns
TIOGSRQ
Time from asserting the Global Set Reset (GSR) net to setting/resetting data at the Output pin
8.079.28ns
Notes:
1.2.3.
The numbers in this table are tested using the methodology presented in Table48 and are based on the operating conditions set forth inTable32 and Table35.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table47.For minimums, use the values reported by the Xilinx timing analyzer.
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2S30-6FG456I中文规格书 - 图文
