Chapter 1:Configuration Overview
Configuration Data File Formats
Xilinx design tools can generate configuration data files in a number of different formats, as described in Table1-3. BitGen converts the post-PAR NCD file into a configuration file or a bitstream. PROMGen, the PROM file generator, converts one or more bitstream files into a PROM file. PROM files can be generated in a number of different file formats and does not need to be used with a PROM. They can be stored anywhere and delivered by any means.
Table 1-3:
Xilinx Configuration File Formats
Xilinx Software
Tool(2)
Description
File
BitSwapping(1)
ExtensionBIT
Not BitSwappedNot BitSwapped?BitGen: NotBitSwapped?PROMGen:BitSwappedBitSwappedDetermined byUser
Binary configuration data file containing header information
BitGen (generated by
that does not need to be downloaded to the FPGA. Used to
default)
program devices from iMPACT with a programming cable. BitGen (generated if ASCII equivalent of the BIT file containing a text header and -b option is set)ASCII 1s and 0s. (Eight bits per configuration bit.)BitGen (generated if -g binary:yesoption is set) orPROMGenPROMGen or iMPACTPROMGen or iMPACT
Binary configuration data file with no header information. Similar to BIT file. Can be used for custom configuration solutions (for example, microprocessors), or in some cases to program third-party PROMs.
ASCII PROM file formats containing address and checksum information in addition to configuration data. Used mainly for device programmers and iMPACT.
ASCII PROM file format containing only configuration data. Used mainly in custom configuration solutions.
RBT
BIN
MCSEXOTEKHEX
Notes:
1.Bit swapping is discussed in the “Bit Swapping” section.
2.For complete BitGen and PROMGen syntax, refer to the Development System Reference Guide.
Bitstream Overview
The Virtex-5 bitstream contains commands to the FPGA configuration logic as well as configuration data. Table1-4 gives a typical bitstream length for each of the Virtex-5 devices.
Table 1-4:Virtex-5 FPGA Bitstream Length
DeviceXC5VLX30XC5VLX50XC5VLX85XC5VLX110XC5VLX155XC5VLX220XC5VLX330
Total Number of Configuration Bits(1)
8,374,01612,556,67221,845,63229,124,60841,048,06453,139,45679,704,832
Virtex-5 FPGA Configuration Guide
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Chapter 1:Configuration Overview
Virtex-5 FPGA Configuration Guide
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Chapter 2:Configuration Interfaces
4.5.6.7.8.9.
The PROM in this diagram represents one or more Xilinx PROMs. Multiple PROMscan be cascaded to increase the overall configuration storage capacity.
The BIT file must be reformatted into a PROM file before it can be stored on thePROM. Refer to the “Generating PROM Files” section.
On some Xilinx PROMs, the reset polarity is programmable. RESET should beconfigured as active Low when using this setup.
For ganged serial configuration, all devices must be identical (same IDCODE) andmust be configured with the same bitstream.
The CCLK net requires Thevenin parallel termination. See “Board Layout forConfiguration Clock (CCLK),” page73.
Ganged serial configuration is specific to the Platform Flash XCFS and XCFP PROMonly.
10.Fallback and Multiboot are not supported in ganged serial configuration.There are a number of important considerations for ganged serial configuration:?
Startup Sequencing (GTS)
GTS should be released before DONE or during the same cycle as DONE to ensure alldevices are operational when all DONE pins have been released.?
Disable the Active DONE Driver for All Devices
For ganged serial configuration, the active DONE driver must be disabled for alldevices if the DONE pins are tied together, because there can be variations in thestartup sequencing of each device. A pull-up resistor is therefore required on thecommon DONE signal.
-g DriveDone:no (BitGen option, all devices)?
Connect all DONE pins if using a Master Device
It is important to connect the DONE pins for all devices in ganged serial configurationif one FPGA is used as the Master device. Failing to connect the DONE pins can causeconfiguration to fail for individual devices in this case. If all devices are set for Slaveserial mode, the DONE pins can be disconnected (if the external CCLK sourcecontinues toggling until all DONE pins go High).
For debugging purposes, it is often helpful to have a way of disconnecting individualDONE pins from the common DONE signal.?
DONE Pin Rise Time
After all DONE pins are released, the DONE pin should rise from logic 0 to logic 1 inone CCLK cycle. If additional time is required for the DONE signal to rise, the BitGendonepipe option can be set for all devices in the serial daisy chain.?
Configuration Clock (CCLK) as Clock Signal for Board Layout
The CCLK signal is relatively slow, but the edge rates on the Virtex-5 input buffers arevery fast. Even minor signal integrity problems on the CCLK signal can cause theconfiguration to fail. (Typical failure mode: DONE Low and INIT_B High.) Therefore,design practices that focus on signal integrity, including signal integrity simulationwith IBIS, are recommended.?
Signal Fanout
Designers must focus on good signal integrity when using ganged serialconfiguration. Signal integrity simulation is recommended.?
PROM Files for Ganged Serial Configuration
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
SelectMAP Configuration Interface
PROM files for ganged serial configuration are identical to the PROM files used to configure single devices. There are no special PROM file considerations.
SelectMAP Configuration Interface
The SelectMAP configuration interface (Figure2-6) provides an 8-bit, 16-bit, or 32-bit bidirectional data bus interface to the Virtex-5 configuration logic that can be used for both configuration and readback. (For details, refer to Chapter7, “Readback and Configuration Verification.”) The bus width of SelectMAP is automatically detected (see “Bus Width Auto Detection”).
CCLK is an output in Master SelectMAP mode; in Slave SelectMAP, CCLK is an input. One or more Virtex-5 devices can be configured through the SelectMAP bus.There are four methods of configuring an FPGA in SelectMAP mode:????
Single device Master SelectMAPSingle device Slave SelectMAPMultiple device SelectMAP busMultiple device ganged SelectMAP
M[2:0] D[31:0]INIT_B PROGRAM_BRDWR_B CS_B DONE CCLK UG191_c2_10_072407
BUSY CSO_BFigure 2-6:Virtex-5 Device SelectMAP Configuration Interface
Table2-4 describes the SelectMAP configuration interface.
Table 2-4:Virtex-5 Device SelectMAP Configuration Interface PinsPin Name
M[2:0]CCLK
Type
InputInput and OutputThree-State Bidirectional
Dedicated or Dual-Purpose
DedicatedDedicatedDual-Purpose
Description
Mode pins - determine configuration modeConfiguration clock source for all configuration modes except JTAG
D[31:0]
Configuration and readback data bus, clocked on the rising edge of CCLK. See “Parallel Bus Bit Order” and Table1-2.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
FPGA可编程逻辑器件芯片XC2V80-5FF1517I中文规格书 - 图文
