Chapter1
Introduction to the RocketIO GTX Transceiver
Overview
The RocketIO? GTX transceiver is a power-efficient transceiver for Virtex?-5 FPGAs. The GTX transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides the following features to support a wide variety of applications:???
Current Mode Logic (CML) serial drivers/buffers with configurable termination,voltage swing, and coupling.
Programmable TX pre-emphasis, RX equalization, and linear and decision feedbackequalization (DFE) for optimized signal integrity.
Line rates from 750Mb/s to 6.5Gb/s, with optional 5x digital oversampling requiredfor rates between 150Mb/s and 750Mb/s. The nominal operation range of the sharedPMA PLL is from 1.5GHz to 3.25GHz. These are nominal values, see DS202: Virtex-5FPGA Data Sheet for specifications.
Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channelbonding, and clock correction.
Fixed latency modes for minimized, deterministic datapath latency.
Beacon signaling for PCI Express? designs and Out-of-Band signaling includingCOM signal support for SATA designs.
RX/TX Gearbox provides header insertion and extraction support for 64B/66B and64B/67B (Interlaken) protocols.Receiver eye scan:
??
?????
Vertical eye scan in the voltage domain for testing purposesHorizontal eye scan in the time domain for testing purposes
The first-time user is recommended to read High-Speed Serial I/O Made Simple [Ref1], which discusses high-speed serial transceiver technology and its applications.
Table1-1 lists some of the standard protocols designers can implement using the GTX transceiver. The Xilinx? CORE Generator? tool includes a Wizard to automatically configure GTX transceivers to support one of these protocols or perform custom configuration (see Chapter2, “RocketIO GTX Transceiver Wizard”).
The GTX_DUAL tile offers a data rate range and features that allow physical layer support for various protocols as illustrated in Table1-1.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Ports and Attributes
Table 1-5:GTX_DUAL Attribute Summary (Cont’d)Attribute
Type
Description
Section (Page)
RX_XCLK_SEL_0RX_XCLK_SEL_1
String
Selects which clock is used on the PMA side of the RX elastic buffer. The
Configurable RX Elastic
default setting is RXREC (RX
Buffer and Phase
recovered clock). Use RXUSR
Alignment (page206)
(RXUSRCLK) when bypassing the RX elastic buffer.
Enables the RX Gearbox.
RX Gearbox (page232)
RXGEARBOX_USE_0RXGEARBOX_USE_1SATA_BURST_VAL_0SATA_BURST_VAL_1SATA_IDLE_VAL_0SATA_IDLE_VAL_1SATA_MAX_BURST_0SATA_MAX_BURST_1SATA_MAX_INIT_0SATA_MAX_INIT_1SATA_MAX_WAKE_0SATA_MAX_WAKE_1SATA_MIN_BURST_0SATA_MIN_BURST_1SATA_MIN_INIT_0SATA_MIN_INIT_1SATA_MIN_WAKE_0SATA_MIN_WAKE_1SIM_GTXRESET_SPEEDUP
Boolean3-bitBinary3-bitBinaryInteger
Number of bursts required for the
RX OOB/Beacon Signaling
SATA OOB detector to declare a COM
(page175)
match.
Number of idles required for the SATA RX OOB/Beacon Signaling OOB detector to declare a COM match.(page175)Sets the threshold for the SATA detector to reject a burst in terms of squelch clock cycles.
Sets the maximum time allowed for a COMINIT/COMRESET idle for the SATA detector in terms of squelch clock cycles.
RX OOB/Beacon Signaling (page175)
Integer
RX OOB/Beacon Signaling (page175)
Integer
Sets the maximum time allowed for a
RX OOB/Beacon Signaling
COMWAKE idle for the SATA detector
(page175)
in terms of squelch clock cycles.Sets the threshold for the SATA detector to reject a burst in terms of squelch clock cycles.
Sets the minimum time allowed for a COMINIT/COMRESET idle for the SATA detector in terms of squelch clock cycles.
RX OOB/Beacon Signaling (page176)
Integer
Integer
RX OOB/Beacon Signaling (page176)
Integer
Sets the minimum time allowed for a
RX OOB/Beacon Signaling
COMWAKE idle for the SATA detector
(page176)
in terms of squelch clock cycles.Shortens the time it takes to finish the GTXRESET sequence and PLL lock during simulation.
Simulation (page54)
Integer
SIM_MODEString
This simulation-only attribute chooses between FAST and LEGACY Simulation (page54)simulation models.
Specifies the length of one symbol in picoseconds for simulation.
Controls the receiver detect modeling in simulation and is intended for PCI Express designs only.
Simulation (page54)
SIM_PLL_PERDIV2
SIM_RECEIVER_DETECT_PASS0SIM_RECEIVER_DETECT_PASS1
9-bit Hex
BooleanSimulation (page54)
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Description
Description
The behavior of the GTX_DUAL tile is modeled using a SmartModel. The SmartModel allows the design containing GTX_DUAL tiles to be simulated in the following design phases:?????
Register Transfer Level (RTL)/Pre-Synthesis SimulationPost-Synthesis Simulation/Pre-NGDBuild SimulationPost-NGDBuild/Pre-Map SimulationPost-Map/Partial Timing SimulationPost-Place and Route/Timing Simulation
Limitations
The analog nature of some blocks inside the GTX_DUAL tile generates some restrictions when simulated using an HDL simulator. Receiver detection and OOB/beacon signaling are analog features of the GTX_DUAL tile that can only be modeled in a limited way with an HDL simulator. The shared PMA PLL is another analog block in the GTX_DUAL tile that is difficult to model precisely. The simulation-only attributes
SIM_GTXRESET_SPEEDUP and SIM_PLL_PERDIV2 speed up the simulation by shortening the locking time of the shared PMA PLL.
SmartModel Attributes
SIM_GTXRESET_SPEEDUP
The SIM_GTXRESET_SPEEDUP attribute can be used to shorten the simulated lock time of the shared PMA PLL.
If TXOUTCLK or RXRECCLK is used to generate clocks in the design, these clocks occasionally flatline while the GTX_DUAL tile is locking. If a PLL or a digital clock
manager (DCM) is used to divide TXOUTCLK or RXRECCLK, the final output clock is not ready until both the GTX_DUAL tile and the PLL or DCM have locked. Equation3-1 provides an estimate of the time required before a stable source from TXOUTCLK or
RXRECCLK is available in simulation, including the time required for any PLLs or DCMs used.
tUSRCLKstable?tGTXRESETsequence+tlocktimePLL+tlocktimeDCMEquation3-1If either the PLL or the DCM is not used, the respective term can be removed from the lock time equation. When simulating multirate designs where the shared PMA PLL frequency or REFCLK frequency changes, SIM_GTXRESET_SPEEDUP must be set to FALSE. AppendixF, “Advanced Clocking” illustrates multirate design examples.
SIM_MODE
This simulation-only attribute chooses between two available UNISIM/SIMPRIM
simulation models. The LEGACY setting selects the legacy simulation model of the PMA of the GTX transceiver. The FAST setting selects a faster simulation model of the PMA of the GTX transceiver to cut simulation run time.
The Legacy model is available for existing users who have been using simulation models with ISE? 11.1 and older software for their designs; however, this legacy model will be
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC2S15-6FGG256C中文规格书 - 图文
