Related Documentation
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Virtex-5 Family Overview or the Virtex-5Q Family Overview
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The features and product selection of the Virtex-5 family are outlined in thisoverview.
?Virtex-5 FPGA User GuideThis guide includes chapters on:
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Clocking Resources
Clock Management Technology (CMT)Phase-Locked Loops (PLLs)Block RAM
Configurable Logic Blocks (CLBs)SelectIO? ResourcesSelectIO Logic Resources
Advanced SelectIO Logic Resources
?Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for theVirtex-5 family.
?Virtex-5 FPGA RocketIO GTP Transceiver User Guide
This guide describes the RocketIO? GTP transceivers available in the Virtex-5 LXTand SXT platforms.
?Virtex-5 FPGA RocketIO GTX Transceiver User Guide
This guide describes the RocketIO GTX transceivers available in the Virtex-5 TXT andFXT platforms.
?Virtex-5 FPGA Embedded Processor Block for Virtex-5 FPGAs
This reference guide is a description of the embedded processor block available in theVirtex-5 FXT platform.
?Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This guide describes the dedicated Tri-Mode Ethernet Media Access Controlleravailable in the Virtex-5 LXT, SXT, TXT and FXT platforms.
?Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express DesignsThis guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, TXT andFXT platforms used for PCI Express? designs.
?Virtex-5 FPGA XtremeDSP Design Considerations
This guide describes the XtremeDSP? slice and includes reference designs for usingthe DSP48E slice.
Virtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)
August 9, 2024
Chapter 2:Pinout Tables
Table 2-2:FF324 Package—LX30 and LX50 (Continued)
Virtex-5 FPGA Packaging and Pinout Specification
FF324 Package—LX30 and LX50
Table 2-2:FF324 Package—LX30 and LX50 (Continued)
Bank44444444441111111111111111111111111111111111111111111111
Pin Description
Pin Number
U10U9R12T12V11V10U11T11R11R10C15C16A13A14B14B15B16A16D14E14A17A18C13B13B18C17F14G14F16E16E17D17D15
No Connect (NC)
IO_L5P_GC_4 IO_L5N_GC_4(1)IO_L6P_GC_4 IO_L6N_GC_4(1) IO_L7P_GC_VRN_4 IO_L7N_GC_VRP_4(1)IO_L8P_CC_GC_4 IO_L8N_CC_GC_4(1)(2)IO_L9P_CC_GC_4 IO_L9N_CC_GC_4(1)(2) IO_L0P_11 IO_L0N_11 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 IO_L5N_11 IO_L6P_11 IO_L6N_11 IO_L7P_11 IO_L7N_11 IO_L8P_CC_11 IO_L8N_CC_11(2) IO_L9P_CC_11 IO_L9N_CC_11(2) IO_L10P_CC_SM15P_11 IO_L10N_CC_SM15N_11(2) IO_L11P_CC_SM14P_11
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 4:Mechanical Drawings
FF665, FFG665, EF665, FFV665 Flip-Chip Fine-Pitch
BGA Package Specifications (1.00mm Pitch)
X-Ref Target - Figure 4-3ug195_c4_ff/ffg/ef/ffv665_042518Figure 4-3: FF665, FFG665, EF665, FFV665 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)
August 9, 2024
Chapter 4:Mechanical Drawings
FF1153 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm Pitch)
X-Ref Target - Figure 4-7ug195_c4_05_100909Figure 4-7:FF1153 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)
August 9, 2024
FPGA可编程逻辑器件芯片XC6VLX75T-2FFG784C中文规格书 - 图文
