DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Electrical Characteristics
Defense-grade Virtex?-5Q FPGAs are available in -2I, -1I, and -1M (only FX70T and FX100T devices in -1M) speed grades, with -2I having the highest performance. Virtex-5Q FPGA DC and AC characteristics are specified for the industrial temperature range. Except the operating
temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The
parameters included are common to popular designs and typical applications.
This Virtex-5Q FPGA data sheet, part of an overall set of documentation on the Virtex-5 family of FPGAs, is available on the Xilinx website:???
DS174, Virtex-5Q Family OverviewUG190, Virtex-5 FPGA User GuideUG191, Virtex-5 FPGA Configuration Guide
?????????
UG192, Virtex-5 FPGA System Monitor User GuideUG193, Virtex-5 FPGA XtremeDSP? DesignConsiderations User Guide
UG194, Virtex-5 FPGA Embedded Tri-Mode EthernetMAC User Guide
UG195, Virtex-5 FPGA Packaging and PinoutSpecification
UG196, Virtex-5 FPGA RocketIO? GTP TransceiverUser Guide
UG197, Virtex-5 FPGA Integrated Endpoint Block UserGuide for PCI Express? Designs
UG198, Virtex-5 FPGA RocketIO GTX TransceiverUser Guide
UG200, Embedded Processor Block in Virtex-5 FPGAsReference Guide
UG203, Virtex-5 FPGA PCB Designer’s Guide
All specifications are subject to change without notice.
Virtex-5Q FPGA DC Characteristics
Table 1:Absolute Maximum Ratings(1)
SymbolVCCINTVCCAUXVCCOVBATTVREF
Description
Internal supply voltage relative to GNDAuxiliary supply voltage relative to GNDOutput drivers supply voltage relative to GNDKey memory battery backup supplyInput reference voltage
3.3V I/O input voltage relative to GND(2) (user and dedicated I/Os)
3.3V I/O input voltage relative to GND (restricted to maximum of 100 user I/Os)(4)2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)
Range–0.5 to 1.1–0.5 to 3.0–0.5 to 3.75–0.5 to 4.05–0.5 to 3.75–0.75 to 4.05–0.85 to 4.3
(Industrial Temperature)
UnitsVVVVVVVVmAmAVV°C
VIN(3)
–0.75 to VCCO+0.5
±100±100–0.75 to 4.05–0.75 to VCCO+0.5
–65to150
IINVTSTSTG
Current applied to an I/O pin, powered or unpoweredTotal current applied to all I/O pins, powered or unpoweredVoltage applied to 3-state 3.3V output(2) (user and dedicated I/Os)Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os)Storage temperature (ambient)
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 68:Block RAM and FIFO Switching Characteristics
Symbol
Block RAM and FIFO Clock to Out DelaysTRCKO_DO and TRCKO_DOR(1)
Clock CLK to DOUT output (without output register)(2)(3)Clock CLK to DOUT output (with output register)(4)(5)Clock CLK to DOUT output with ECC (without output register)(2)(3)
Clock CLK to DOUT output with ECC (with output register)(4)(5)
Clock CLK to DOUT output with Cascade (without output register)(2)
Clock CLK to DOUT output with Cascade (with output register)(4)
TRCKO_FLAGSTRCKO_POINTERSTRCKO_ECCRTRCKO_ECC
Clock CLK to FIFO flags outputs(6)Clock CLK to FIFO pointer outputs(7)Clock CLK to BITERR (with output register)Clock CLK to BITERR (without output register)Clock CLK to ECCPARITY in standard ECC modeClock CLK to ECCPARITY in ECC encode only mode
1.920.693.030.772.441.070.871.260.772.851.470.89
2.190.823.610.932.941.301.021.480.933.411.741.05
2.190.823.610.932.941.301.021.480.933.411.741.05
ns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Max
Description
Speed Grade-2I
-1I
-1M
Units
Setup and Hold Times Before/After Clock CLKTRCCK_ADDR/TRCKC_ADDRTRDCK_DI/TRCKD_DI
ADDR inputs(8)DIN inputs(9)
DIN inputs with ECC in standard mode(9)
TRDCK_DI_ECC/TRCKD_DI_ECC
DIN inputs with ECC encode only(9)
TRCCK_EN/TRCKC_EN
TRCCK_REGCE/TRCKC_REGCETRCCK_SSR/TRCKC_SSRTRCCK_WE/TRCKC_WETRCCK_WREN/TRCKC_WREN
Block RAM Enable (EN) inputCE input of output register
Synchronous Set/ Reset (SSR) inputWrite Enable (WE) input WREN/RDEN FIFO inputs(10)
0.400.320.300.280.370.330.720.330.360.150.160.240.210.250.510.170.410.34
0.480.360.350.290.420.360.770.360.420.150.180.270.260.280.630.180.480.40
0.480.360.350.290.420.470.770.470.420.150.180.270.260.280.630.180.480.40
ns, Minns, Minns, Minns, Minns, Minns, Minns, Minns, Minns, Min
Reset DelaysTRCO_FLAGS
Reset RST to FIFO Flags/Pointers(11)
1.26
1.48
1.48
ns, Max
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 68:Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol
Maximum FrequencyFMAX
FMAX_CASCADEFMAX_FIFOFMAX_ECCNotes:
1.2.3.4.5.6.7.8.9.10.11.
TRACE will report all of these parameters as TRCKO_DO.
TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.These parameters also apply to synchronous FIFO with DO_REG=0.
TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG=1.
TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B.These parameters also apply to RDEN.
TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
Description
Speed Grade-2I500450500375
-1I450400450325
-1M450400450325
Units
Block RAM in all modes
Block RAM in cascade configurationFIFO in all modes
Block RAM and FIFO in ECC configuration
MHzMHzMHzMHz
DSP48E Switching Characteristics
Table 69:DSP48E Switching Characteristics
Symbol
Description
Speed Grade-2I0.210.230.160.31
-1I0.260.300.200.37
-1M0.260.300.200.50
Units
Setup and Hold Times of Data/Control Pins to the Input Register ClockTDSPDCK_{AA, BB, ACINA, BCINB}/TDSPCKD_{AA, BB, ACINA, BCINB}TDSPDCK_CC/TDSPCKD_CC
{A, B, ACIN, BCIN} input to {A, B} register CLK C input to Cregister CLK
nsns
Setup and Hold Times of Data Pins to the Pipeline Register ClockTDSPDCK_{AM, BM, ACINM, BCINM}/TDSPCKD_{AM, BM, ACINM, BCINM}
{A, B, ACIN, BCIN} input to Mregister CLK
1.440.19
1.710.19
1.710.19
ns
Setup and Hold Times of Data/Control Pins to the Output Register ClockTDSPDCK_{AP, BP, ACINP, BCINP}_M/TDSPCKD_{AP, BP, ACINP, BCINP}_MTDSPDCK_{AP, BP, ACINP, BCINP}_NM/TDSPCKD_{AP, BP, ACINP, BCINP}_NMTDSPDCK_CP/TDSPCKD_CPTDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/
TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP}
{A, B, ACIN, BCIN} input to Pregister CLK using multiplier
{A, B, ACIN, BCIN} input to Pregister CLK not using multiplier
C input to Pregister CLK
{PCIN, CARRYCASCIN, MULTSIGNIN} input to Pregister CLK
2.74–0.301.54–0.101.42–0.131.170.11
3.25–0.301.83–0.101.70–0.131.310.11
3.25–0.301.83–0.101.70–0.131.310.11
nsnsnsns
Setup and Hold Times of the CE Pins
{CEA1, CEA2A, CEB1B, CEB2B} input to TDSPCCK_{CEA1A, CEA2A, CEB1B,
{A,B} register CLKCEB2B}/
TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}TDSPCCK_CECC/TDSPCKC_CECCTDSPCCK_CEMM/TDSPCKC_CEMM
CEC input to Cregister CLKCEM input to Mregister CLK
0.280.250.210.210.290.21
0.330.310.260.280.360.26
0.330.310.260.280.360.26
ns
nsns
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 70:Configuration Switching Characteristics (Cont’d)
Symbol
BPI Master Flash Mode Programming SwitchingTBPICCO(4)TBPIDCC/TBPICCDTINITADDR
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs valid after CCLK rising edge
Setup/Hold on D[15:0] data input pins
Minimum period of initial ADDR[25:0] address cycles
103.00.53.0
103.00.53.0
103.00.53.0
nsnsCCLK cycles
Description
Speed Grade-2I
-1I
-1M
Units
SPI Master Flash Mode Programming SwitchingTSPIDCC/TSPIDCCDTSPICCMTSPICCFCTFSINIT/TFSINITH
DIN Setup/Hold before/after the rising CCLK edgeMOSI clock to outFCS_B clock to out
FS[2:0] to INIT_B rising edge Setup and Hold
4.00.010102
4.00.010102
5.00.010102
nsnsnsμs
CCLK Output (Master Modes)TMCCKLTMCCKH
Master CCLK clock minimum Low timeMaster CCLK clock minimum High time
3.03.0
3.03.0
3.03.0
ns, Minns, Min
CCLK Input (Slave Modes)TSCCKLTSCCKHFDCK
TDMCCK_DADDR/TDMCKC_DADDRTDMCCK_DI/TDMCKC_DITDMCCK_DEN/TDMCKC_DENTDMCCK_DWE/TDMCKC_DWETDMCKO_DOTDMCKO_DRDYNotes:
1.2.3.4.
Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages.
To support longer delays in configuration, use the design solutions described in the Virtex-5 FPGA User Guide.DO will hold until next DRP operation.
Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
Slave CCLK clock minimum Low timeSlave CCLK clock minimum High time
2.02.0
2.02.0
2.02.0
ns, Minns, Min
Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK
Maximum frequency for DCLKDADDR Setup/HoldDI Setup/HoldDEN Setup/Hold timeDWE Setup/Hold timeCLK to out of DO(3)CLK to out of DRDY
4501.350.01.350.01.350.01.350.01.121.12
4001.560.01.560.01.560.01.560.01.301.30
4001.560.01.560.01.560.01.560.01.301.30
MHznsnsnsnsnsns
DS714 (v2.2) January 17, 2011Product Specification
FPGA可编程逻辑器件芯片XCZU9EG-L1FFVB1156I中文规格书 - 图文
