Thermal Specifications
Summary
This chapter provides thermal data associated with Virtex-6 FPGA packages. The following topics are discussed:??????
Introduction
Thermal Management StrategySome Thermal Management OptionsSupport for Compact Thermal Models (CTM)Soldering GuidelinesReferences
Introduction
Virtex-6 devices are offered exclusively in thermally efficient flip-chip BGA packages. These 1.0 mm flip-chip packages range in pin-count from the smaller 23x23mm FF484 to the 45x45mm FF1924. The suite of packages is used to address the various power
requirements of the Virtex-6 devices. All Virtex-6 devices are implemented in the 40nm process technology.
Similar to Virtex-5 FPGAs, all Virtex-6 devices feature versatile SelectIO? resources that support a variety of I/O standards. They also include a System Monitor, DSPs, and other traditional features and blocks (such as block RAM) contained in earlier Virtex products.In line with Moore's law, the transistor count in this family of devices has been increased substantially. Though several innovative features at the silicon level have been deployed to minimize power dissipation, including leakage at the 40nm node, these products have more densely packed transistors and embedded blocks with the capability to run faster than before. Thus, a fully configured Virtex-6 FPGA design that exploits the fabric speed and incorporates several embedded circuits and systems can present power consumption challenges that must be managed.
Unlike features in an ASIC or a microprocessor, the combination of FPGA features used in a user application are not known to the component supplier. Therefore, it remains a
challenge for Xilinx to predict the power requirements of a given FPGA when it leaves the factory. Accurate estimates are obtained when the board design takes shape. For this purpose, Xilinx offers and supports a suite of integrated device power analysis tools to help users quickly and accurately estimate their design power requirements. Virtex-6 devices are supported similarly to previous FPGA products. The uncertainty of design power requirements makes it difficult to apply canned thermal solutions to fit all users. Therefore, Xilinx devices do not come with preset thermal solutions. The user’s operating conditions dictate the appropriate solution.
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
Chapter 4:Mechanical Drawings
RF784 Flip-Chip Fine-Pitch BGA Package Specifications
(1.00mm Pitch)
X-Ref Target - Figure 4-3ug365_c4_13_11111Figure 4-3:RF784 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
Chapter 5:Package
FF484FFG484
Thermal SpecificationsPackageBody Size
23x23
Devices
XC6VLX75TXC6VLX130TXC6VLX75T
θJA(°C/W)
13.112.611.811.210.910.8
θJB(°C/W)
3.53.13.53.12.92.7
θJC(°C/W)
0.280.170.280.170.140.11
θJA (°C/W)@ 250 LFM
8.98.37.57.17.06.8
θJA (°C/W)@ 500 LFM
7.47.06.46.05.85.7
θJA (°C/W)@ 750 LFM
6.86.45.85.45.35.2
FF784FFG784RF784
29x29
XC6VLX130TXQ6VLX130TXC6VLX195TXC6VLX240TXQ6VLX240T
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
Chapter 4:Mechanical Drawings
RF1156 Flip-Chip Fine-Pitch BGA Package Specifications
(1.00mm Pitch)
X-Ref Target - Figure 4-7ug365_c4_14_11111Figure 4-7:RF1156 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
FF1923 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm Pitch)
FF1923 Flip-Chip Fine-Pitch BGA Package Specifications
(1.00mm Pitch)
X-Ref Target - Figure 4-12ug365_c4_08_100209Figure 4-12:FF1923 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
FPGA可编程逻辑器件芯片XC6VSX315T-2FFG1156C中文规格书 - 图文
