10.Hot Socketing and Power-On Reset in
StratixIII Devices
SIII51010-1.7
This chapter describes information about hot-socketing specifications, power-on reset (POR) requirements, and their implementation in Stratix?III devices.
StratixIII devices offer hot socketing, also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. You can insert or remove a StratixIII device or a board in a system during system operation without causing undesirable effects to the running system bus or board that is inserted into the system.
The hot socketing feature also removes some of the difficulty when you use StratixIII devices on PCBs that contain a mixture of 3.3-, 3.0-, 2.5-, 1.8-, 1.5-, and 1.2-V devices. With the StratixIII hot socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board.The StratixIII hot-socketing feature provides:
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Board or device insertion and removal without external components or boardmanipulation
Support for any power-up sequence
I/O buffers non-intrusive to system buses during hot insertion
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This section also describes the POR circuitry in StratixIII devices. POR circuitry keeps the devices in the reset state until the power supplies are within operating range.
StratixIII Hot-Socketing Specifications
StratixIII devices are hot-socketing compliant without the need for external components or special design requirements. Hot socketing support in StratixIII devices has the following advantages:
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You can drive the device before power-up without damaging it.
I/O pins remain tri-stated during power-up. The device does not drive out beforeor during power-up, thereby not affecting other buses in operation.
You can insert a StratixIII device into or remove it from a powered-up systemboard without damaging or interfering with normal system/board operation.
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StratixIII Devices Can Be Driven Before Power Up
You can drive signals into I/O pins, dedicated input pins, and dedicated clock pins of StratixIII devices before or during power up or power down without damaging the device. StratixIII devices support power up or power down of the power supplies in any sequence in order to simplify system-level design.
Stratix III Device Handbook, Volume 1
Chapter 9:High-Speed Differential I/O Interfaces and DPA in StratixIII DevicesClocking
Stratix III Device Handbook, Volume 1
Chapter 10:Hot Socketing and Power-On Reset in StratixIII Devices
Hot-Socketing Feature Implementation in StratixIII Devices
I/O Pins Remain Tri-Stated During Power Up
A device that does not support hot socketing can interrupt system operation or cause contention by driving out before or during power up. In a hot-socketing situation, the StratixIII device's output buffers are turned off during system power up or power down. Also, the StratixIII device does not drive out until the device is configured and working within recommended operating conditions.
Insertion or Removal of a StratixIII Device from a Powered-Up System
Devices that do not support hot socketing can short power supplies when powered up through the device signal pins. This irregular power up can damage both the driving and driven devices and can disrupt card power up.
You can insert a StratixIII device into or remove it from a powered-up system board without damaging the system board or interfering with its operation.
You can power up or power down the core voltage supplies (VCC, VCCL, VCCPT, VCCA_PLL, and VCCD_PLL), VCCIO, VCCPMG, VCC_CLKIN, and VCCPD supplies in any sequence and at any time between them. The individual power supply ramp-up and ramp-down rates can range from 50μs to 12ms or 100ms depending on the PORSEL setting. During hot socketing, the I/O pin capacitance is less than 15pF and the clock pin capacitance is less than 20pF.
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For more information about the hot socketing specification, refer to the DC and Switching Characteristics of StratixIII Devices chapter and the Hot-Socketing and Power-Sequencing Feature and Testing for Altera Devices White Paper.
A possible concern regarding hot socketing is the potential for “latch-up”.
Nevertheless, StratixIII devices are immune to latch-up when hot socketing. Latch-up can occur when electrical subsystems are hot socketed into an active system. During hot socketing, the signal pins can be connected and driven by the active system before the power supply can provide current to the device's power and ground planes. This condition can lead to latch-up and cause a low-impedance path from power to ground within the device. As a result, the device draws a large amount of current, possibly causing electrical damage.
Hot-Socketing Feature Implementation in StratixIII Devices
The hot-socketing feature turns off the output buffer during power up and power down of the VCC, VCCIO, VCCPGM, or VCCPD power supplies. The hot-socketing circuitry generates an internal HOTSCKT signal when the VCC, VCCIO, VCCPGM, or VCCPD power supplies are below the threshold voltage. Hot-socketing circuitry is designed to prevent excess I/O leakage during power up. When the voltage ramps up very slowly, it is still relatively low, even after the POR signal is released and the configuration is completed. The CONF_DONE, nCEO, and nSTATUS pins fail to
respond, as the output buffer cannot flip from the state set by the hot-socketing circuit at this low voltage. Therefore, the hot-socketing circuit has been removed on these configuration pins to make sure that they are able to operate during configuration. Thus, it is expected behavior for these pins to drive out during power-up and power-down sequences.
Stratix III Device Handbook, Volume 1
Chapter 11:Configuring StratixIII Devices
Configuration Devices
Table11–1.StratixIII Configuration Schemes
Configuration SchemeFast passive parallel (FPP)Passive serial (PS)Fast AS (40 MHz) (1)Remote system upgrade fast AS (40 MHz) (1)FPP with design security feature, decompression, or both enabled (2)JTAG-based configuration (4)Notes to Table11–1:
(1)To support fast AS configuration for StratixIII, you must use EPCS16, EPCS64, or EPCS128 devices. For more
information, refer to Serial Configuration Devices Data Sheet chapter.
(2)These modes are only supported when using a MAX?II device or a microprocessor with flash memory for
configuration. In these modes, the host system must output a DCLK that is ×4 the data rate.
(3)Do not leave the MSEL pins floating. Connect them to VCCPGM or ground. These pins support the non-JTAG
configuration scheme used in production. If you only use JTAG configuration, connect the MSEL pins to ground.(4)JTAG-based configuration takes precedence over other configuration schemes, which means MSEL pin settings
are ignored.
MSEL200000(3)MSEL101110(3)MSEL000111(3)Table11–2 lists the uncompressed raw binary file (.rbf) configuration file sizes for StratixIII devices.
Table11–2.StratixIII Uncompressed Raw Binary File (.rbf) Sizes
Device EP3SL50EP3SL70EP3SL110EP3SL150EP3SL200EP3SL340EP3SE50EP3SE80EP3SE110EP3SE260Data Size (Bits)22, 178, 79222, 178, 79247, 413, 31247, 413, 31293, 324, 656117, 387, 66425, 891, 96848, 225, 39248, 225, 39293, 324, 656Use the data in Table11–2 to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal (.hex) or tabular text file (.ttf) format, have different file sizes. Refer to the Quartus?II software for the different types of configuration file and the file sizes. However, for any specific version of the QuartusII software, any design targeted for the same device will have the same uncompressed configuration file size. If you are using compression, the file size can vary after each compilation because the compression ratio is dependent on the design.
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For more information about setting device configuration options or creating configuration files, refer to the Device Configuration Options and Configuration File Formats chapters in volume 2 of the Configuration Handbook.
Stratix III Device Handbook, Volume 1
Chapter 11:Configuring StratixIII DevicesConfiguration Features
Stratix III Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP2S180F1508I3N中文规格书 - 图文
