Feature Descriptions
SGMII GTX Transceiver Clock Generation
[Figure1-2, callout 16]
An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter, 125MHz LVDS clock from a 25MHz crystal (X3). This clock is sent to FPGA U1, Bank 113 GTX
transceiver (clock pins AH8 (P) and AH7 (N)) driving the SGMII interface. Series AC coupling capacitors are present to allow the clock input of the FPGA to set the common mode voltage. Figure1-17 shows the Ethernet SGMII clock source.
X-Ref Target - Figure 1-17C30018pF 50VNPOVDDA_SGMIICLKVDD_SGMIICLKU2X325.00 MHz1X11SGMIICLK_XTAL_OUT3ICS844021I-01Clock GeneratorOEVDDAXTAL_OUTVDDQ0587SGMIICLK_Q0_C_PR3201.0MΩ 5?0118pF 50VNPO2GND2C280.1μF 25VX5RSGMIICLK_Q0_P4GND2X23SGMIICLK_XTAL_IN42XTAL_INGNDNQ06SGMIICLK_Q0_C_NSGMIICLK_Q0_NC290.1μF 25VX5RUG885_c1_17_020612GND_SGMIICLKGND_SGMIICLKGND_SGMIICLKFigure 1-17:Ethernet 125 MHz SGMII GTX Clock
References
Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode Ethernet MAC Product Guide for Vivado Design Suite (PG051) [Ref9] and in the LogiCORE IP Tri-Mode Ethernet MAC v4.5 User Guide (UG138) [Ref13].
The product brief for the Marvell 88E1111 Alaska Gigabit Ethernet Transceiver can be found at the Marvell website [Ref21].
The data sheet can be obtained under NDA with Marvell. Contact information is at the Marvell website [Ref21].
For more information about the ICS844021 device, go to the Integrated Device Technology website [Ref22] and search for part number ICS844021.
USB-to-UART Bridge
[Figure1-2, callout 17]
The VC707 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U44) which allows a connection to a host computer with a USB port. The USB cable is supplied in the VC707 Evaluation Kit (Type-A end to host computer, Type mini-B end to VC707 board connector J17). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the VC707 board.
Xilinx UART IP is expected to be implemented in the FPGA logic. The FPGA supports the
USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications application software (for example, TeraTerm) that runs on the host computer. The VCP device
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Feature Descriptions
User SMA
Figure1-28 shows the user SMA circuit.
X-Ref Target - Figure 1-28J33SMAConnectorUSER SMA GPIO PGNDJ34SMAConnectorUSER SMA GPIO NGNDUG885_c1_126_012413Figure 1-28:User SMA
Table1-26 lists the GPIO Connections to FPGA U1.Table 1-26:
GPIO Connections to FPGA U1
Schematic Net Name
I/O Standard
GPIO Pin
FPGA (U1) Pin
Indicator LEDs (Active-High)AM39AN39AR37AT37AR35AP41AP42AU39
GPIO_LED_0GPIO_LED_1GPIO_LED_2GPIO_LED_3GPIO_LED_4GPIO_LED_5GPIO_LED_6GPIO_LED_7
LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18LVCMOS18
DS2.2DS3.2DS4.2DS5.2DS6.2DS7.2DS8.2DS9.2
CPU Reset Pushbutton SwitchAV40
CPU_RESET
LVCMOS18
SW8.3
Directional Pushbutton SwitchesAR40AU38AP40
GPIO_SW_NGPIO_SW_EGPIO_SW_S
LVCMOS18LVCMOS18LVCMOS18
SW3.3SW4.3SW5.3
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Feature Descriptions
Table1-32 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 54 (U64).
Table 1-32:
Power Rail Specifications for UCD9248 PMBus Controller at Address 54
Shutdown Threshold(1)
IOUT Over Fault (A)Temp Over Fault (°C)90909090
VOUT Over Fault (V)2.31.152.072.07
Nominal VOUT (V)PGOff Threshold (V)PGOn Threshold (V)Rise Time (ms)Off Delay (ms)On Delay (ms)RailNumberRailNameSchematicRail Name
1234
Rail #1Rail #2Rail #3Rail #4
VCCAUX_IOVCC_BRAMMGTVCCAUXVCC1V8_FPGA
211.81.8
1.80.91.621.62
1.70.851.531.53
0000
5555
2975
Fall Time (ms)1111
10.4110.4110.4110.41
Notes:
1.The values defined in these columns are the voltage, current, and temperature thresholds that cause the regulator to shut down if the value isexceeded.
FPGA Cooling Fan Operation
The FPGA cooling fan control circuit has its PWM signal wired to a dual-use FPGA Bank15 pin BA37. After configuration, this pin is expected to be toggled by user-provided fan speed control IP to control fan speed.
FPGA U1 pin BA37 is alternately an unused BPI flash memory address pin (A28). During FPGA configuration in BPI mode, the BPI flash memory address lines are driven. The BA37 pin is held low during BPI configuration and thus the fan PWM signal is not active. The FPGA U1 cooling fan is off during the FPGA BPI configuration process.
After configuration is complete, the dual-use FPGA pin BA37 is available for use by user-provided fan speed control IP.
References
More information about the power system components used by the VC707 board are available from the Texas Instruments digital power website [Ref25].
PCIe Form Factor Board TI Power System Cooling
If the power modules on the VC707 board are operating at moderate to high current levels (due to a customer design), the modules can generate substantial heat, which can cause them to shut down without warning. The power module shutdown then turns off the FPGA on the development board. Refer to the Virtex-7FPGA VC707 Evaluation Kit Master Answer Record in AppendixG: References for more information.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Appendix C:Xilinx Constraints File
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
FPGA可编程逻辑器件芯片XC2V80-5FG256C中文规格书 - 图文
