Chapter3
Boundary-Scan and JTAG Configuration
Introduction
Spartan?-6 devices support IEEE Std 1149.1, defining Test Access Port (TAP) and
boundary-scan architecture. These standards ensure the board-level integrity of individual components and the interconnections between them. In addition to connectivity testing, boundary-scan architecture offers flexibility for vendor-specific instructions, such as configure and verify, which add the capability of loading configuration data directly to FPGAs and compliant memories. TAP and boundary-scan architecture is commonly referred to collectively as JTAG.
Boundary-Scan for Spartan-6 Devices Using IEEE Std 1149.1
The Spartan-6 family is fully compliant with the IEEE Std 1149.1 (TAP and boundary-scan architecture). The architecture includes all mandatory elements defined in IEEE Std 1149.1. These elements include the TAP, the TAP controller, the Instruction register, the instruction decoder, the boundary-scan register, and the BYPASS register. The Spartan-6 family also supports a 32-bit Identification register in full compliance with the standard. Outlined in the following sections are the details of the JTAG architecture for Spartan-6 devices. More details about the JTAG architecture for Spartan-6devices can be found in Chapter10, Advanced JTAG Configurations.
Test Access Port (TAP)
The Spartan-6 FPGA TAP contains four mandatory dedicated pins as specified by the protocol in Spartan-6 devices and in typical JTAG architecture (see Figure10-1, page162). Three input pins and one output pin control the IEEE Std 1149.1 boundary-scan TAP controller. Optional control pins, such as Test Reset (TRST), and enable pins might be found on devices from other manufacturers. It is important to be aware of these optional signals when interfacing Xilinx devices with parts from different vendors because they might need to be driven.
The IEEE Std 1149.1 boundary-scan TAP controller is a state machine (16 states), shown in Chapter10, Advanced JTAG Configurations.
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Chapter 3:Boundary-Scan and JTAG Configuration
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Chapter 4:User Primitives
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Generating PROM Files
Parallel Bus Bit Order
Traditionally, in SelectMAP x8 mode, configuration data is loaded one byte per CCLK, with the most-significant bit (MSB) of each byte presented to the D0 pin. Although this convention (D0 = MSB, D7 = LSB) differs from many other devices, it is consistent across all Xilinx FPGAs. The bit-swap rule also applies to Spartan-6 FPGA BPI x8 modes (see Bit Swapping, page80).
In Spartan-6 devices, the bit-swap rule is extended to x16 bus widths; the data is bit swapped within each byte.
Table5-8 and Table5-9 show examples of a sync word inside a bitstream. These examples illustrate what is expected at the FPGA data pins when using parallel configuration modes, such as Slave SelectMAP and Master SelectMAP (BPI) modes.Table 5-8:Sync Word Bit Swap Example
Sync Word
Bitstream FormatBit Swapped
Notes:
1.[31:24] changes from 0xAA to 0x55 after bit swapping.
[31:24](1)0xAA0x55
[23:16]0x990x99
[15:8]0x550xAA
[7:0]0x660x66
Table 5-9:Sync Word Data Sequence Example for x8 and x16 Modes
CCLK CycleD[7:0] pins for x8 D[15:0] pins for x16
10x550x5599
20x990xAA66
30xAA
40x66
Delaying Configuration
There are two ways to delay configuration for Spartan-6 devices:??
Table 5-10:
Hold the INIT_B pin Low during initialization. When INIT_B has gone High,configuration cannot be delayed by subsequently pulling INIT_B Low.
Hold the PROGRAM_B pin Low. The signals relating to initialization and delayingconfiguration are defined in Table5-10.
Access(1)
Externally accessible via the PROGRAM_B pin.
Signals Relating to Initialization and Delaying Configuration
TypeInput
Description
Global asynchronous chip reset. Can be held Low to delay configuration.
Before the Mode pins are sampled, INIT_B is an input that can be held Low to delay configuration.
After the Mode pins are sampled, INIT_B is an open-drain, active-Low output that indicates whether a CRC error occurred during configuration or a readback CRC error occurred after configuration (when enabled):0 = CRC error
1 = No CRC error (needs an external pull-up)
Signal NamePROGRAM_BINIT_B
Input, Externally accessible via the Output, INIT_B pin.or Open Drain
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Chapter 5:Configuration Details
Table 5-10:Signals Relating to Initialization and Delaying Configuration (Cont’d)
TypeStatus
Access(1)
Internal signals, accessible through the Spartan-6 FPGA status register.
Description
Reflects the direct pin value of the Mode pins.
Signal NameMODE_STATUS[1:0]
Notes:
1.Information on the Spartan-6 FPGA status register is available in Table5-38, page107. Information on accessing the device statusregister via JTAG is available in Table6-5, page124. Information on accessing the device status register via SelectMAP is available in Table6-1.
2.The Status type is an internal status signal without a corresponding pin.
Configuration Sequence
While each of the configuration interfaces is different, the basic steps for configuring a Spartan-6 device are the same for all modes. Figure5-2 shows the Spartan-6 FPGA
configuration process. The following subsections describe each step in detail, where the current step is highlighted in gray at the beginning of each subsection.
X-Ref Target - Figure 5-2Steps1DevicePower-Up2ClearConfigurationMemory3Sample ModePins4Synchronization5Device IDCheck6LoadConfigurationData7CRC Check8StartupSequenceSetupStartBitstreamLoadingFinishUG380_c5_02_042909Figure 5-2:Spartan-6 FPGA Configuration Process
The Spartan-6 device is initialized and the configuration mode is determined by sampling the mode pins in three setup steps.
Setup (Steps 1-3)
The setup process is similar for all configuration modes (see Figure5-3).
The setup steps are critical for proper device configuration. The steps include Device Power-Up, Clear Configuration Memory, and Sample Mode Pins.
Device Power-Up (Step 1)
X-Ref Target - Figure 5-3Steps1DevicePower-Up2ClearConfigurationMemory3Sample ModePins4Synchronization5Device IDCheck6LoadConfigurationData7CRC Check8StartupSequenceSetupStartBitstreamLoadingFinishUG380_c5_03_042909Figure 5-3:Device Power-Up (Step 1)
For configuration, Spartan-6 devices require power at least on the VCCO_2, VCCAUX, and VCCINT pins, plus any other VCCO banks used during configuration. There are no power-
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FPGA可编程逻辑器件芯片XC2S200-4FGG256I中文规格书 - 图文
