半导体传感器AD7685BRMZ中文规格书 - 图文

AD7710

USING THE AD7710SYSTEM DESIGN CONSIDERATIONSAccuracyThe AD7710 operates differently from successive approxima-tion ADCs or integrating ADCs. Because it samples the signalcontinuously, like a tracking ADC, there is no need for a startconvert command. The output register is updated at a ratedetermined by the first notch of the filter, and the output can beread at any time, either synchronously or asynchronously.ClockingThe AD7710 requires a master clock input, which may be anexternal TTL/CMOS compatible clock signal applied to theMCLK IN pin with the MCLK OUT pin left unconnected.Alternatively, a crystal of the correct frequency can be connectedbetween MCLK IN and MCLK OUT, in which case the clockcircuit will function as a crystal-controlled oscillator. For lowerclock frequencies, a ceramic resonator may be used instead ofthe crystal. For these lower frequency oscillators, externalcapacitors may be required on either the ceramic resonator oron the crystal.The input sampling frequency, the modulator sampling fre-quency, the –3 dB frequency, the output update rate, and thecalibration time are all directly related to the master clock fre-quency fCLK IN. Reducing the master clock frequency by a factorof 2 will halve the above frequencies and update rate and willdouble the calibration time.The current drawn from the DVDD power supply is also directlyrelated to fCLK IN. Reducing fCLK IN by a factor of 2 will halve theDVDD current but will not affect the current drawn from theAVDD power supply.System SynchronizationSigma-delta ADCs, like VFCs and other integrating ADCs, donot contain any source of nonmonotonicity and inherently offerno missing codes performance. The AD7710 achieves excellentlinearity by the use of high quality, on-chip silicon dioxidecapacitors, which have a very low capacitance/voltage coefficient.The device also achieves low input drift through the use of chopperstabilized techniques in its input stage. To ensure excellent perfor-mance over time and temperature, the AD7710 uses digitalcalibration techniques that minimize offset and gain error.AutocalibrationAutocalibration on the AD7710 removes offset and gain errorsfrom the device. A calibration routine should be initiated on thedevice whenever there is a change in the ambient operatingtemperature or supply voltage. It should also be initiated if thereis a change in the selected gain, filter notch, or bipolar/unipolarinput range. However, if the AD7710 is in its background cali-bration mode, these changes are all automatically taken care of(after the settling time of the filter has been allowed for).The AD7710 offers self-calibration, system calibration, andbackground calibration facilities. For calibration to occur on theselected channel, the on-chip microcontroller must record themodulator output for two different input conditions. These arezero-scale and full-scale points. With these readings, the micro-controller can calculate the gain slope for the input to outputtransfer function of the converter. Internally, the part workswith a resolution of 33 bits to determine its conversion result ofeither 16 bits or 24 bits.The AD7710 also provides the facility to write to the on-chipcalibration registers, and, in this manner, the span and offset forthe part can be adjusted by the user. The offset calibration regis-ter contains a value that is subtracted from all conversionresults, while the full-scale calibration register contains a valuethat is multiplied by all conversion results. The offset calibrationcoefficient is subtracted from the result prior to the multiplica-tion by the full-scale coefficient. In the first three modes out-lined here, the DRDY line indicates that calibration is completeby going low. If DRDY is low before (or goes low during) thecalibration command, it may take up to one modulator cyclebefore DRDY goes high to indicate that calibration is inprogress. Therefore, DRDY should be ignored for up to onemodulator cycle after the last bit of the calibration command iswritten to the control register.Self-CalibrationIf multiple AD7710s are operated from a common master clock,they can be synchronized to update their output registers simul-taneously. A falling edge on the SYNC input resets the filter andplaces the AD7710 into a consistent, known state. A commonsignal to the AD7710s’ SYNC inputs will synchronize theiroperation. This would typically be done after each AD7710 hasperformed its own calibration or has had calibration coefficientsloaded to it.The SYNC input can also be used to reset the digital filter insystems where the turn-on time of the digital power supply(DVDD) is very long. In such cases, the AD7710 will start oper-ating internally before the DVDD line has reached its minimumoperating level, 4.75 V. With a low DVDD voltage, theAD7710’s internal digital filter logic does not operate correctly.Thus, the AD7710 may have clocked itself into an incorrectoperating condition by the time that DVDD has reached its cor-rect level. The digital filter will be reset upon issue of a calibra-tion command (whether it is self-calibration, system calibration,or background calibration) to the AD7710. This ensures correctoperation of the AD7710. In systems where the power-ondefault conditions of the AD7710 are acceptable, and no cali-bration is performed after power-on, issuing a SYNC pulse tothe AD7710 will reset the AD7710’s digital filter logic. An R, Con the SYNC line, with R, C time constant longer than theDVDD power-on time, will perform the SYNC function.In the self-calibration mode with a unipolar input range, thezero-scale point used in determining the calibration coefficientsis with both inputs shorted (that is, AIN(+) = AIN(–) = VBIAS)and the full-scale point is VREF. The zero-scale coefficient isdetermined by converting an internal shorted inputs node. Thefull-scale coefficient is determined from the span between thisshorted inputs conversion and a conversion on an internal VREFnode. The self-calibration mode is invoked by writing the appro-priate values (0, 0, 1) to the MD2, MD1, and MD0 bits of thecontrol register. In this calibration mode, the shorted inputsnode is switched in to the modulator first and a conversion isREV. G–17–

AD7710

performed; the VREF node is then switched in and another conver-sion is performed. When the calibration sequence is complete, thecalibration coefficients updated, and the filter resettled to the ana-log input voltage, the DRDY output goes low. The self-calibrationprocedure takes into account the selected gain on the PGA.For bipolar input ranges in the self-calibrating mode, thesequence is very similar to that just outlined. In this case, thetwo points that the AD7710 calibrates are midscale (bipolarzero) and positive full scale.System CalibrationSystem calibration can also be used to remove any errors froman antialiasing filter on the analog input. A simple R, C anti-aliasing filter on the front end may introduce a gain error on theanalog input voltage but the system calibration can be used toremove this error.System Offset CalibrationSystem calibration allows the AD7710 to compensate forsystem gain and offset errors as well as its own internal errors.System calibration performs the same slope factor calculationsas self-calibration but uses voltage values presented by the sys-tem to the AIN inputs for the zero- and full-scale points. Systemcalibration is a two-step process. The zero-scale point must bepresented to the converter first. It must be applied to the con-verter before the calibration step is initiated and remain stableuntil the step is complete. System calibration is initiated bywriting the appropriate values (0, 1, 0) to the MD2, MD1,MD0 bits of the control register. The DRDY output from thedevice will signal when the step is complete by going low. Afterthe zero-scale point is calibrated, the full-scale point is applied,and the second step of the calibration process is initiated byagain writing the appropriate values (0, 1, 1) to MD2, MD1,MD0. Again the full-scale voltage must be set up before thecalibration is initiated, and it must remain stable throughout thecalibration step. DRDY goes low at the end of this second stepto indicate that the system calibration is complete. In the uni-polar mode, the system calibration is performed between thetwo endpoints of the transfer function; in the bipolar mode, it isperformed between midscale and positive full scale.This two-step system calibration mode offers another feature.After the sequence has been completed, additional offset or gaincalibrations can be performed by themselves to adjust the zeroreference point or the system gain. This is achieved by perform-ing the first step of the system calibration sequence (by writing0, 1, 0 to MD2, MD1, MD0). This will adjust the zero-scale oroffset point but will not change the slope factor from that setduring a full system calibration sequence.System offset calibration is a variation of both the system cali-bration and self-calibration. In this case, the zero-scale pointfor the system is presented to the AIN input of the converter.System offset calibration is initiated by writing 1, 0, 0 to MD2,MD1, MD0. The system zero-scale coefficient is determined byconverting the voltage applied to the AIN input, while the full-scale coefficient is determined from the span between this AINconversion and a conversion on VREF. The zero-scale pointshould be applied to the AIN input for the duration of the cali-bration sequence. This is a one-step calibration sequence withDRDY going low when the sequence is completed. In unipolarmode, the system offset calibration is performed between thetwo endpoints of the transfer function; in bipolar mode, it isperformed between midscale and positive full scale.Background CalibrationThe AD7710 also offers a background calibration mode wherethe part interleaves its calibration procedure with its normalconversion sequence. In background calibration mode, the samevoltages are used as the calibration points that are used in theself-calibration mode, that is, shorted inputs and VREF. Thebackground calibration mode is invoked by writing 1, 0, 1 toMD2, MD1, MD0 of the control register. When invoked, thebackground calibration mode reduces the output data rate of theAD7710 by a factor of 6 while the –3 dB bandwidth remainsunchanged. The advantage is that the part is continually per-forming calibration and automatically updating its calibrationcoefficients. As a result, the effects of temperature drift, sup-ply sensitivity, and time drift on zero- and full-scale errors areautomatically removed. When the background calibration modeis turned on, the part will remain in this mode until bits MD2,MD1, and MD0 of the control register are changed. With back-ground calibration mode on, the first result from the AD7710will be incorrect because the full-scale calibration will not havebeen performed. For a step change on the input, the secondoutput update will have settled to 100% of the final value.Table VI summarizes the calibration modes and the calibrationpoints associated with them. It also gives the duration fromwhen the calibration is invoked to when valid data is available tothe user.Table VI.Calibration Truth TableCal TypeSelf-CalSystem CalSystem CalSystem Offset CalBackground CalMD2, MD1, MD00, 0, 10, 1, 00, 1, 11, 0, 01, 0, 1Zero-Scale CalShorted InputsAINAINShorted InputsFull-Scale CalVREFAINVREFVREFSequenceOne StepTwo StepsTwo StepsOne StepOne StepDuration9 × 1/Output Rate4 × 1/Output Rate4 × 1/Output Rate9 × 1/Output Rate6 × 1/Output Rate–18–REV. G