Configuration Interfaces
Virtex?-5 devices have six configuration interfaces. Each configuration interface
corresponds to one or more configuration modes and bus width, shown in Table2-1. For detailed interface timing information, see DS202, Virtex-5 FPGA Data Sheet: DC and Switching Characteristic.
Table 2-1:Virtex-5 Device Configuration Modes
Configuration ModeMaster Serial(2)Master SPI(2)Master BPI-Up(2)Master BPI-Down(2)Master SelectMAP(2)JTAG
Slave SelectMAPSlave Serial
Notes:
1.Parallel configuration mode bus is auto-detected by the configuration logic.
2.In Master configuration mode, the CCLK pin is the clock source for the Virtex-5 internal configuration logic. The Virtex-5 CCLK output pin must be free from reflections to avoid double-clocking the
internal configuration logic. Refer to the “Board Layout for Configuration Clock (CCLK)” section formore details.
M[2:0]000001010011100101110111
Bus Width
118, 168, 168, 1618, 16, 32
1
CCLK Direction
OutputOutputOutputOutputOutputInput (TCK)InputInput
Serial Configuration Interface
In serial configuration modes, the FPGA is configured by loading one configuration bit per CCLK cycle:??
In Master Serial mode, CCLK is an output.In Slave Serial mode, CCLK is an input.
Figure2-1 shows the basic Virtex-5 serial configuration interface.There are four methods of configuring an FPGA in serial mode:???
Master serial configurationSlave serial configurationSerial daisy-chain configuration
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 2:Configuration Interfaces
Parallel Daisy Chain
Virtex-5 FPGA configuration supports parallel daisy-chain. Figure2-12 shows an example schematic of the leading device in BPI mode. The leading device can also be in Master or Slave SelectMAP modes. The D[15:0], CCLK, RDWR_B, PROGRAM_B, DONE, and INIT_B pins share a common connection between all of the devices. The CS_B pins are daisy chained.
4.7 kΩ330Ω330Ω330ΩA[25:0]D[15:0]FlashFCS_BFOE_BFWE_BBUSYCSO_BINIT_BDONEPROGVirtex-5A[25:0]FPGAD[15:0]FCS_BFOE_BFWE_BCCLKM2M1M0010BUSYCSO_BINIT_BDONEPROGVirtex-5FPGAD[15:0]CS_BRDWR_BCCLKM2M1M0110BUSYNoCSO_BINIT_BConnectDONEPROGD[15:0]CS_BVirtex-5FPGARDWR_BCCLKM2M1M0110BPI UPM[2:0]=Slave SelectMAPM[2:0]=Slave SelectMAP
UG191_c2_14_081910
Figure 2-12:
Notes relevant to Figure2-12:1.2.3.4.5.6.
Parallel Daisy Chain
The DONE pin is by default an open-drain output requiring an external pull-upresistor. In this arrangement, the active DONE driver must be disabled.
The INIT_B pin is a bidirectional, open-drain pin. An external pull-up is required.The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.The BUSY signals can be left unconnected if readback is not needed.The CCLK net requires Thevenin parallel termination. See “Board Layout forConfiguration Clock (CCLK).”
The FCS_B, FWE_B, FOE_B, CSO_B weak pull-up resistors should be enabled,otherwise external pull-up resistors are required for each pin. By default, all dual-mode I/Os have weak pull-downs after configuration.
The first device in the chain can be Master SelectMAP, Slave SelectMAP, BPI-Up, orBPI-Down.
Readback in the parallel daisy chain scheme is currently not supported.AES decryption is not available in x16 or x32 mode, only in x8 mode.
7.8.9.
10.Fallback is not supported in parallel daisy-chain.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
SelectMAP Configuration Interface
Ganged SelectMAP
It is also possible to configure simultaneously multiple devices with the same configuration bitstream by using a ganged SelectMAP configuration. In a ganged
SelectMAP arrangement, the CS_B pins of two or more devices are connected together (or tied to ground), causing all devices to recognize data presented on the D pins.
All devices can be set for Slave SelectMAP mode if an external oscillator is available, or one device can be designated as the Master device, as illustrated in Figure2-13.
M1M2M0DATA[0:7]CCLKCFCERESET/OEVirtex-5 FPGASelectMAPMasterD[0:7]CCLKPROGRAM_BBUSYINIT_BRDWR_B(1)330Ω
DONEXilinxPlatform Flash PROMCS_BM1M2M0(10)Virtex-5 FPGASelectMAPSlaveD[0:7]CCLKPROGRAM_BBUSYINIT_B(2)4.7 kΩ(10)RDWR_BCS_BDONEUG191_c2_15_041808
Figure 2-13:
Notes relevant to Figure2-13:1.
Ganged x8 SelectMAP Configuration
The DONE pin is by default an open-drain output requiring an external pull-upresistor. In this arrangement, the active DONE driver must be disabled for bothdevices.
The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor isrequired.
The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.The BUSY signal is not used for ganged SelectMAP configuration.
The PROM in this diagram represents one or more Xilinx PROMs. Multiple XilinxPROMs can be cascaded to increase the overall configurations storage capacity.The BIT file must be reformatted into a PROM file before it can be stored on the XilinxPROM. Refer to the “Generating PROM Files” section.
2.3.4.5.6.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
SelectMAP Configuration Interface
CCLK
CS_BRDWR_B
DATA[0:7]STATUSBUSY
ABORT
ug191_c2_19_092507
Figure 2-17:Configuration Abort Sequence for SelectMAP Modes
Readback Abort Sequence Description
An ABORT is signaled during readback as follows:1.2.3.4.
The readback sequence begins normally.
The user pulls the RDWR_B pin Low while the device is selected (CS_B asserted Low).BUSY goes High if CS_B remains asserted (Low).The ABORT ends when CS_B is deasserted.
CCLKCS_BRDWR_B
DATA[0:7]FPGABUSY
ABORTUG191_c2_20_041006Figure 2-18:Readback Abort Sequence
ABORTs during readback are not followed by a status word because the RDWR_B signal is set for write control (FPGA D[x:0] pins are inputs).
ABORT Status Word
During the configuration ABORT sequence, the device drives a status word onto the D[7:0] pins. The status bits do not bit-swap. The other data pins are always High. The key for that status word is given in Table2-5.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
FPGA可编程逻辑器件芯片XQR4VSX55-10CN1140V中文规格书 - 图文
