Chapter1
Configuration Overview
Overview
Spartan?-6 FPGAs are configured by loading application-specific configuration data—a bitstream—into internal memory. Spartan-6 FPGAs can load themselves from an external nonvolatile memory device or they can be configured by an external smart source, such as a microprocessor, DSP processor, microcontroller, PC, or board tester. In any case, there are two general configuration datapaths. The first is the serial datapath that is used to
minimize the device pin requirements. The second datapath is the 8- or 16-bit datapath used for higher performance or access (or link) to industry-standard interfaces, ideal for external data sources like processors, or x8- or x16-parallel flash memory.
Like processors and processor peripherals, Xilinx? FPGAs can be reprogrammed, in system, on demand, an unlimited number of times.
Because Xilinx FPGA configuration data is stored in CMOS configuration latches (CCLs), it must be reconfigured after it is powered down. The bitstream is loaded each time into the device through special configuration pins. These configuration pins serve as the interface for a number of different configuration modes:?????
JTAG configuration mode
Master Serial/SPI configuration mode (x1, x2, and x4)Slave Serial configuration mode
Master SelectMAP/BPI configuration mode (x8 and x16)Slave SelectMAP configuration mode (x8 and x16)
The configuration modes are explained in detail in Chapter2, Configuration Interface Basics.
The specific configuration mode is selected by setting the appropriate level on the mode input pins M[1:0]. The M1 and M0 mode pins should be set at a constant DC voltage level and tied directly to ground or VCCO_2. The mode pins should not be toggled during or before configuration but can be toggled after. See Chapter2, Configuration Interface Basics, for the mode pin setting options.
The terms Master and Slave refer to the direction of the configuration clock (CCLK):?
In Master configuration modes, the Spartan-6 device drives CCLK from an internaloscillator by default or optional external master clock source GCLK0/USERCCLK. Toselect the desired frequency, the BitGen -g ConfigRate option is used for theinternal oscillator. The default is 2MHz. The CCLK output frequency varies withprocess, voltage, and temperature. The data sheet FMCCKTOL specification defines thefrequency tolerance. A frequency tolerance of ±50% means that a ConfigRate settingof 10 could generate a CCLK rate of between 5MHz and 15MHz.The BitGen section
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 2:Configuration Interface Basics
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 3:Boundary-Scan and JTAG Configuration
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 6:Readback and Configuration Verification
Table 6-2:Step11
Shutdown Readback Command Sequence (SelectMAP) (Cont’d)SelectMAP PortDirection
Read
Configuration Data
0000...000030A1
Packet Data Read FDRO Last WordType 1 Write 1 Word to CMDLFRM CommandType 1 NOOP Word 0Type 1 Write 1 Word to CMDSTART CommandType 1 NOOP Word 0Type 1 NOOP Word 0Type 1 NOOP Word 0Type 1 NOOP Word 0Type 1 Write 1 Word to CMDRCRC CommandType 1 NOOP Word 0Type 1 Write 1 Word to CMDDESYNC Command
Type 1 NOOP Word 0
REPEAT for at least 16 cycles.
Explanation
Packet Data Read FDRO Word 0
12Write0003200030A10005200020002000200030A1
13Write
14Write0007200030A1000D2000
1516
WriteWrite
User logic should strobe readback data while DOUT_BUSY is Low after switching from a write to a read (both CSI_B and RDWR_B are Low). DOUT_BUSY must be monitored to determine when the readback data is valid.
When readback is initiated, and after BUSY is deasserted, a number of dummy words depending on the SelectMAP bus width are read prior to valid data behind present. Table6-3 lists the dummy readback cycles for the two SelectMAP widths.Table 6-3:Readback Latency (SelectMAP)
x8
CSI_B to Readback Latency
Notes:
1.These latencies assume CSI_B and RDWR_B are deasserted for one cycle between write and read. Ifthe deassertion lasts more than one cycle, then the latency is less. It is best to monitor the BUSY signal for valid readback data.
x162 clocks
3 clocks
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Readback Command Sequences
Accessing Configuration Registers through the JTAG Interface
JTAG access to the Spartan-6 FPGA configuration logic is provided through the JTAG CFG_IN and CFG_OUT registers. The CFG_IN and CFG_OUT registers are not configuration registers, rather they are JTAG registers like BYPASS and
BOUNDARY_SCAN. Data shifted into the CFG_IN register goes to the configuration packet processor, where it is processed in the same way commands from the SelectMAP interface are processed.
Readback commands are written to the configuration logic by going through the CFG_IN register; configuration memory is read through the CFG_OUT register. The JTAG state transitions for accessing the CFG_IN and CFG_OUT registers are described in Table6-4.
Table 6-4:Step
1234
Shifting in the JTAG CFG_IN and CFG_OUT Instructions
Description
Set and HoldTDI
XXXX000101 (CFG_IN)000100 (CFG_OUT)
0XXX
TMS
1010
# of Clocks (TCK)
5122
Clock five 1s on TMS to bring the device to the TLR stateMove into the RTI stateMove into the Select-IR stateMove into the Shift-IR state
Shift the first five bits of the CFG_IN or CFG_OUT instruction, LSB first
Shift the MSB of the CFG_IN or CFG_OUT instruction while exiting SHIFT-IR
Move into the SELECT-DR stateMove into the SHIFT-DR state
Shift data into the CFG_IN register or out of the CFG_OUT register while in SHIFT_DR, MSB first
505
6789
1100
122X
1011
Shift the LSB while exiting SHIFT-DRReset the TAP by clocking five 1s on TMS
XX
11
15
Configuration Register Read Procedure (JTAG)
The simplest read operation targets a configuration register such as the COR0 or STAT register. Any configuration register with read access can be read through the JTAG
interface, although not all registers offer read access. The procedure for reading the STAT register through the JTAG interface follows:1.2.
Reset the TAP controller.
Shift the CFG_IN instruction into the JTAG Instruction Register through the Shift-IRstate. The LSB of the CFG_IN instruction is shifted first; the MSB is shifted whilemoving the TAP controller out of the SHIFT-IR state.
Shift packet write commands into the CFG_IN register through the Shift-DR state:a.b.c.
Write the synchronization word to the device.
Write the read STAT register packet header to the device.
Write two dummy words to the device to flush the packet buffer.
3.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
FPGA可编程逻辑器件芯片XC2V80-6FF1152C中文规格书 - 图文
