Chapter 2: XPHY Architecture
?Requires SELF_CALIBRATE = ENABLE
?Quarter (QTR) delays: QTR delays are applied to the p-clk and n-clk. This is in contrast toCRSE delays, which are applied to the strobe. Cannot be controlled through the PL. For moreinformation on the p-clk and n-clk, see Clocking.?Requires SELF_CALIBRATE = ENABLE
Controlling Delays
Input and output delays can be changed through the PL, as shown in the following table.Table 7: Controlling Input and Output Delays
RX_EN_VTCTX_EN_VTC
LD
000
0
01111
CE
00110011
INC
01010101
Stays the sameStays the sameDecrement by 1 tapIncrement by 1 tap
Effect on Delay Line
Load value from CNTVALUEINLoad value from CNTVALUEINNot supported
Add value from CNTVALUEIN to the current CNTVALUEOUT value
The following table shows how the delay-related signals are mapped to each NIBBLESLICE.
Table 8: Delay Control Signals NIBBLESLICE Mapping
Port
CE[5:0]INC[5:0]LD[5:0]RXTX_SEL[5:0]
NIBBLESLICE[5]NIBBLESLICE[4]NIBBLESLICE[3]NIBBLESLICE[2]NIBBLESLICE[1]NIBBLESLICE[0]
CE[5]INC[5]LD[5]RXTX_SEL[5]
CE[4]INC[4]LD[4]RXTX_SEL[4]
CE[3]INC[3]LD[3]RXTX_SEL[3]
CE[2]INC[2]LD[2]RXTX_SEL[2]
CE[1]INC[1]LD[1]RXTX_SEL[1]
CE[0]INC[0]LD[0]RXTX_SEL[0]
Description
Control signalControl signalControl signal
Selects between theinput and output delayline to apply delay lineupdates or report theirtap-value throughCNTVALUEOUT
Number of taps to beapplied to the delay line
Number of taps currentlyused by delay line
CNTVALUEIN[53:0]
CNTVALUEOUT[53:0]
CNTVALUEIN[53:45]
CNTVALUEOUT
[53:45]
CNTVALUEIN[44:36]
CNTVALUEOUT
[44:36]
CNTVALUEIN[35:27]
CNTVALUEOUT
[35:27]
CNTVALUEIN[26:18]
CNTVALUEOUT
[26:18]
CNTVALUEIN
[17:9]
CNTVALUEOUT
[17:9]
CNTVALUEIN
[8:0]
CNTVALUEOUT
[8:0]
AM010 (v1.2) April 2, 2024
Versal ACAP SelectIO Resources Architecture Manual
Chapter 2: XPHY Architecture
Table 9: Delay Attributes
Attribute
CASCADE_<0-5>CRSE_DLY_ENDELAY_VALUE_<0-5>
Description
Doubles the available delay in a NIBBLESLICE by cascading the input and output delays in theNIBBLESLICE. Only applicable for RX.Enables coarse delays
Sets the initial delay for the input and output delays in a NIBBLESLICE. If CASCADE_x = TRUE, the maxdelay available in DELAY_VALUE_x doubles.
DELAY_VALUE_x sets the initial delay (in ps) of both the input and output delay in
NIBBLESLICE[x]. While DELAY_VALUE_x is set in terms of time, the delay is ultimately applied tothe delay lines in terms of taps. This makes DELAY_VALUE_x unique in that it is the only way toset a time value through an attribute for any of the delay lines.
When changing the value of input or output delays, consider the following:?DLY_RDY must be 1.
?To avoid glitches, input and output delays can only be changed once every three CTRL_CLKcycles.?Input and output delay changes take effect one CTRL_CLK cycle after being reflected inCNTVALUEOUT.?Delays, regardless of the type, are always manifested in terms of taps.
?If a nonzero DELAY_VALUE_x is set, the following equation can be used to estimate the
number of taps required for a new time-based value for an input or output delay. Delay_old isthe previous delay in terms of time (ps) whereas delay_new is the desired delay in terms oftime (ps). If DELAY_VALUE_x were set to zero, this equation would not be valid. While
CNTVALUEIN can still be used to load taps, the approximate time value of each tap will not beknown and thus cannot be used to calculate a new time delay value. Align_delay is used byBISC to compensate for the internal skew between clock and data insertion delays of inputpaths to the first capture flip-flops. More information on align_delay can be found beneath thefollowing waveforms and in Built-in Self-Calibration.
CNTVALUEIN[NIBBLESLICE[x]] = delay_new *
((CNTVALUEOUT[NIBBLESLICE[x]] – align_delay)/delay_old)
?Updating input and output delays through the register interface unit (RIU) takes one additionalCTRL_CLK cycle compared to updating delays through the PL. When updating input or outputdelays through the RIU, RX_EN_VTC and TX_EN_VTC must be set to 1, LD must be set to 1,CE must be set to 0, and INC is a don't care. Note that only input and output delays can beupdated through the PL.?If TBYTE_CTRL_# = PHY_WREN, the tristate NIBBESLICE is capable of applying a delay tothe tristate signal. To change the amount of delay applied in the tristate NIBBLESLICE, use theTRISTATE_ODLY register within the RIU.
AM010 (v1.2) April 2, 2024
Versal ACAP SelectIO Resources Architecture Manual
FPGA可编程逻辑器件芯片XC2V1000-6BF957I中文规格书
