Table 39:GTX_DUAL Tile Quiescent Supply Current
SymbolIAVTTTXQIAVCCPLLQIAVTTRXQIAVCCQ
Description
Quiescent MGTAVTTTX (transmitter termination) supply currentQuiescent MGTAVCCPLL (PLL) supply current
Quiescent MGTAVTTRX (receiver termination) supply current. Includes MGTAVTTRXCQ.
Quiescent MGTAVCC (analog) supply current
Typ(1)8.20.81.29.0
Max21.64.812.050.4
UnitsmAmAmAmA
Notes:
1.Typical values are specified at nominal voltage, 25°C.2.Device powered and unconfigured.
3.Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
4.GTX_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number
of available GTX_DUAL tiles in the target FXT device.
GTX_DUAL Tile DC Input and Output Levels
Table40 summarizes the DC output specifications of the GTX_DUAL tiles in Virtex-5Q FPGAs. Figure6, page20 shows the single-ended output voltage swing. Figure7, page20 shows the peak-to-peak differential output voltage.Consult Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further details.Table 40:GTX_DUAL Tile DC Specifications
SymbolDVPPIN
DC ParameterConditionsMin200125–400
TypMax18001800
MGTAVTTRX+400
up to 1320
UnitsmVmVmVmV
External AC coupled
Differential peak-to-peak input ?4.25Gb/svoltage
External AC coupled ?4.25Gb/sAbsolute input voltageCommon mode input voltageDifferential peak-to-peak output voltage(1)
Single-ended output voltage swing(1)
Common mode output voltageDifferential input resistanceDifferential output resistanceTransmitter output skew
Recommended external AC coupling capacitor(2)
DC coupled
MGTAVTTRX=1.2VDC coupled
MGTAVTTRX=1.2VTXBUFDIFFCTRL=111TXBUFDIFFCTRL=111Equation based
MGTAVTTTX=1.2V
VINVCMINDVPPOUTVSEOUTVCMOUTRINROUTTOSKEWCEXTNotes:
1.2.
800
1400700
1200–DVPPOUT/2
858575
1001002100
1201208200
mVmVmV??psnF
The output swing and preemphasis levels are programmable using the attributes discussed in Virtex-5 FPGA RocketIO GTX TransceiverUser Guide and can result in values lower than reported in this table.
Values outside of this range can be used as appropriate to conform to specific protocols and standards.
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Ethernet MAC Switching Characteristics
Consult Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide for further information.Table 49:Maximum Ethernet MAC Performance
SymbolFTEMACCLIENT
Description
Client interface maximum frequency
Conditions
10 Mb/s – 8-bit width100 Mb/s – 8-bit width1000 Mb/s – 8-bit width2000 Mb/s – 16-bit width
Speed Grade-2I1.2512.51251252.525125250
-1I1.2512.51251252.525125250
-1M1.2512.51251252.525125250
UnitsMHzMHzMHzMHzMHzMHzMHzMHz
FTEMACPHY
Physical interface maximum frequency10 Mb/s – 4-bit width100 Mb/s – 4-bit width1000 Mb/s – 8-bit width2000 Mb/s – 8-bit width
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
System Monitor Analog-to-Digital Converter Specification
Table 51:Analog-to-Digital Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
AVDD=2.5V±2%,VREFP=2.5V, VREFN=0V, ADCCLK=5.2MHz, TA=TMIN to TMAX, Typical values at TA=+25°CDC Accuracy: All external input channels such as VP/VN and VAUXP[15:0]/VAUXN[15:0], Unipolar Mode, and Common Mode = 0VResolution
Integral NonlinearityDifferential NonlinearityUnipolar Offset Error(1)Bipolar Offset Error(1)Gain Error(1)
Bipolar Gain Error(1)
INLDNL
No missing codes (TMIN to TMAX)Guaranteed MonotonicUncalibrated
Uncalibrated measured in bipolar mode Uncalibrated, Tj=–40°C to 100°CUncalibrated, Tj=–55°C to 125°CUncalibrated measured in bipolar mode, Tj=–40°C to 100°C
Uncalibrated measured in bipolar mode, Tj=–55°C to 125°C
Total Unadjusted Error(Uncalibrated)Total Unadjusted Error(Calibrated)
Calibrated Gain Temperature Coefficient
DC Common-Mode Reject
CMRRDCTUETUE
Deviation from ideal transfer function.VREFP–VREFN=2.5V
Deviation from ideal transfer function.VREFP–VREFN=2.5V
Variation of FS code with temperatureVN = VCM=0.5V± 0.5V,VP–VN=100mVNumber of CLK cyclesNumber of CLK cyclesNumber of CLK cyclesDRP clock frequency
Derived from DCLK, Tj=–40°C to 100°CDerived from DCLK, Tj=–55°C to 125°C
CLK Duty cycle
4812.540
Unipolar OperationDifferential Inputs
Unipolar Common Mode Range (FS input)Differential Common Mode Range (FS input) Bandwidth
Auxiliary Analog InputsInput Voltage Range
VAUXP[0] /VAUXN[0] to VAUXP[15] /VAUXN[15]
Unipolar OperationDifferential Operation
Unipolar Common Mode Range (FS input)Differential Common Mode Range (FS input)Bandwidth
Input Leakage CurrentInput Capacitance
On-chip Supply Monitor Error
VCCINT and VCCAUX with calibration enabledA/D not converting, ADCCLK stopped
0–0.250+0.3
10±1.010
±1.0
0–0.250+0.3
20
1+0.25+0.5+0.7
kHzμApF%
Reading10
±2±0.9
±2±2±0.2±0.2±0.2±0.2±10±1±0.0170
±2±30±30±2.0±2.5±2.0±2.5
BitsLSBsLSBsLSBsLSBs%%%%LSBsLSBsLSB/°CdB
Conversion Rate(2)
Conversion Time - ContinuousConversion Time - EventT/H Acquisition TimeDRP Clock FrequencyADC Clock Frequency
tCONVtCONVtACQDCLKADCCLK
26
32212505.25.2601+0.25+0.5+0.7
MHzVoltsMHzMHzMHz%V
Analog Inputs(3)Dedicated Analog InputsInput Voltage RangeVP - VN
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Switching Characteristics
All values represented in this data sheet are based on speed specification version1.71. Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows:Advance
These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur.Preliminary
These specifications are based on complete ES
(engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data.Production
These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between
specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades.
All specifications are always representative of worst-case supply voltage and junction temperature conditions.Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device.
Table54 correlates the current status of each Virtex-5Q device on a per speed grade basis.
Table 54:Virtex-5Q Device Speed Grade Designations
DeviceXQ5VLX30TXQ5VLX85XQ5VLX110XQ5VLX110TXQ5VLX155TXQ5VLX220TXQ5VLX330TXQ5VSX50TXQ5VSX95TXQ5VSX240TXQ5VFX70TXQ5VFX100TXQ5VFX130TXQ5VFX200T
Speed Grade Designations
Advance
Preliminary
Production-2I, -1I-2I, -1I-2I, -1I-2I, -1I-2I, -1I-2I, -1I-1I-2I, -1I-2I, -1I-1I-2I, -1I, -1M-2I, -1I, -1M-2I, -1I-1I
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-5Q devices.
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
IOB Pad Input/Output/3-State Switching Characteristics
Table56 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.
TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer.TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer.
TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer.
Table57, page34 summarizes the value of TIOTPHZ.
TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state).
Table 56:IOB Switching Characteristics
TIOPI
I/OStandard
-2(I)
LVDS_25LVDSEXT_25HT_25BLVDS_25
RSDS_25 (point to point)ULVDS_25PCI33_3PCI66_3PCI-XGTLGTLPHSTL_IHSTL_IIHSTL_IIIHSTL_IVHSTL_I _18HSTL_II _18HSTL_III _18HSTL_IV_18SSTL2_ISSTL2_II
LVTTL, Slow, 2mALVTTL, Slow, 4mALVTTL, Slow, 6mALVTTL, Slow, 8mALVTTL, Slow, 12mALVTTL, Slow, 16mALVTTL, Slow, 24mA
0.901.160.900.900.900.900.700.700.700.850.850.850.850.850.850.850.850.850.850.850.850.700.700.700.700.700.700.70
TIOOPSpeed Grade
-1(M)1.111.361.111.121.111.111.051.051.051.111.051.071.051.401.401.261.131.451.451.111.111.021.021.021.021.021.021.02
TIOTPSpeed Grade
-1(M)1.791.821.791.911.791.792.412.412.032.102.141.961.842.032.071.911.791.981.921.941.836.054.133.912.912.562.472.48
Speed Grade
-1(I)1.061.301.061.061.061.060.820.820.821.001.001.001.001.001.001.001.001.001.001.001.000.820.820.820.820.820.820.82
Units
-1(M)1.791.821.791.911.791.792.412.412.032.102.141.961.842.032.071.911.791.981.921.941.836.054.133.912.912.562.472.48
nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
-2(I)1.291.341.261.381.291.272.062.061.561.631.681.571.531.601.601.551.511.611.571.641.554.473.092.912.302.152.042.07
-1(I)1.441.491.401.581.441.412.382.381.801.861.931.791.741.851.831.771.721.851.811.781.765.013.413.292.612.462.342.38
-2(I)1.291.341.261.381.291.272.062.061.561.631.681.571.531.601.601.551.511.611.571.641.554.473.092.912.302.152.042.07
-1(I)1.441.491.401.581.441.412.382.381.801.861.931.791.741.851.831.771.721.851.811.781.765.013.413.292.612.462.342.38
DS714 (v2.2) January 17, 2011Product Specification
FPGA可编程逻辑器件芯片XQR5VFX130-1CF1752V中文规格书 - 图文
