Chapter 1:Configuration Overview
Table 1-16:Default BitGen Sequence of Startup Events
Event
Release DONE pinNegate GTS, activating I/O
Assert GWE, allowing RAMs and flip-flops to change state AssertEOS
Phase
4567
The startup sequence can be forced to wait for the DCMs to lock or for DCI to match with
the appropriate BitGen options. These options are typically set to prevent DONE, GTS, and GWE from being asserted (preventing device operation) before the DCMs have locked and/or DCI has matched.
The DONE signal is released by the startup sequencer on the cycle indicated by the user, but the startup sequencer does not proceed until the DONE pin actually sees a logic High. The DONE pin is an open-drain bidirectional signal by default. By releasing the DONE pin, the device simply stops driving a logic Low and the pin goes into a High-Z state. An external pull-up resistor is needed for the DONE pin to reach a logic High in this case. Table1-17 shows signals relating to the startup sequencer. Figure1-12 shows the waveforms relating to the startup sequencer.
Table 1-17:
Signals Relating to Startup Sequencer
Type
Bidirectional(2)
Access(1)
DONE pin or
Virtex-5 Status Register
Signal Name
DONERelease_DONE
Description
Indicates configuration is complete. Can be held Low externally to synchronize startup with other FPGAs. Indicates whether the device has stopped driving the DONE pin Low. If the pin is held Low externally, Release_DONE can differ from the actual value on the DONE pin.
GWE
Global Write Enable (GWE). When asserted, GWE enables the CLB and the IOB flip-flops as well as other synchronous elements on the FPGA.
Global 3-State (GTS). When asserted, GTS disables all the I/O drivers except for the configuration pins.
Status
GTSEOS
DCI_MATCH
Virtex-5 Status Register
End of Startup (EOS). EOS indicates the absolute end of the configuration and startup process.
DCI_MATCH indicates when all the Digitally Controlled Impedance (DCI) controllers have matched their internal resistor to the external reference resistor.
DCM_LOCK indicates when all the Digital Clock
Managers (DCMs) have locked. This signal is asserted by default. It is active if the LOCK_WAIT option is used on a DCM and the LockCycle option is used when the bitstream is generated.
DCM_LOCK
Notes:
1.Information on the Virtex-5 status register is available in Table6-9. Information on accessing the device status register via JTAG isavailable in Table7-5. Information on accessing the device status register via SelectMAP is available in Table7-1.2.Open-drain output by default; optional driver enabled using the BitGen drivedone option.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Serial Configuration Interface
DONE Pin Rise Time
After all DONE pins are released, the DONE pin should rise from logic 0 to logic 1 in one CCLK cycle. External pull-up resistors are required. If additional time is required for the DONE signal to rise, the BitGen donepipe option can be set for all devices in the serial daisy chain. (Refer to the BitGen section of the Development System Reference Guide for software settings.)
Ganged Serial Configuration
More than one device can be configured simultaneously from the same bitstream using a ganged serial configuration setup (Figure2-5). In this arrangement, the serial configuration pins are tied together such that each device sees the same signal transitions. One device is typically set for Master serial mode (to drive CCLK) while the others are set for Slave serial mode. For ganged serial configuration, all devices must be identical. Configuration can be driven from a configuration PROM or from an external configuration controller.
XilinxPlatform PROMDATACLKCERESET/OE(8)M0M1M2DINCCLKDOUT(8)(1)Virtex-5FPGAMasterSerialPROGRAM_BDONEINIT_B(2)PROGRAMM0M1M2DINCCLKDOUTVirtex-5 FPGASlaveSerialPROGRAM_BDONEINIT_Bug191_c2_31_090808
Figure 2-5:
Notes relevant to Figure2-5:1.
Ganged Serial Configuration
For ganged serial configuration, the optional DONE driver must be disabled for alldevices if one device is set for Master mode because each device might not start up onexactly the same CCLK cycle. An external pull-up resistor is required in this case.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor isrequired.
The BitGen startup clock setting must be set for CCLK for serial configuration.
2.3.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
SelectMAP Configuration Interface
(6)DATA[7:0]CCLKWRITEBUSY(6)M1M0M2M1M0M2Virtex-5SlaveSelectMAPD[7:0]CCLKRDWR_BBUSYCS(0)330Ω(1)(2)4.7 kΩCS_BPROGRAM_BDONEINIT_BCS(1)Virtex-5SlaveSelectMAPD[7:0]CCLKRDWR_BBUSYCS_BPROGRAM_BDONEINIT_BDONEINITPROGRAMUG191_c2_13_072407
Figure 2-11:Multiple Slave Device Configuration on an 8-Bit SelectMAP BusNotes relevant to Figure2-11:
1.The DONE pin is by default an open-drain output requiring an external pull-up
resistor. In this arrangement, the active DONE driver must be disabled.
2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
3.The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.4.The BUSY signals can be left unconnected if readback is not needed.
5.An external controller such as a microprocessor or CPLD is needed to control
configuration.
6.The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page73.7.The data bus can be x8, x16, or x32.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
FPGA可编程逻辑器件芯片XC2S150E-6FGG456C中文规格书 - 图文
