Device/Package Combinations and Maximum I/Os
Table1-1 shows the maximum number of user I/Os possible in Virtex-5 FPGA flip-chip packages. FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
Table 1-1:
Flip-Chip Packages
Packages
FF3241.0019 x 19220
FF6651.0027 x 27360
FF6761.0027 x 27440
FF1136FF11531.0035 x 35640
1.0035 x 35800
FF11561.0035 x 35360
FF17381.0042.5 x 42.5960
FF17591.0042.5 x 42.5680
FF17601.0042.5 x 42.51200
Package
SpecificationsFF323Pitch(mm)Size(mm)Maximum I/Os
1.0019 x 19172
The number of I/Os per package includes all user I/Os except the 19 pins listed in Table1-2.
Table 1-2:Virtex-5 FPGA I/O Pinsin the Dedicated Configuration Bank (Bank0)DXPDXNVBATTPROGRAM_B
HSWAPEND_INDONECCLK_0
INIT_B_0CS_B_0RDWR_B_0TCK_0
M0_0M1_0M2_0TMS
TDI
D_OUT_BUSYTDO_0
The RocketIO? GTP transceiver I/O channels for the devices listed in Table1-3 or the GTX transceiver I/O channels for the devices listed in Table1-4.
Table 1-3:I/O ChannelsMGTRXPMGTRXNMGTTXPMGTTXN
Notes:
1.The XC5VLX30T has 4 GTP I/O channels in the FF323/FFG323 package and 8 GTP I/O channels in the FF665/FFG665 package.2.The XC5VLX50T has 8 GTP I/O channels in the FF665/FFG665 package and 12 GTP I/O channels in the FF1136/FFG1136 package. 3.The XC5VSX50T has 8 GTP I/O channels in the FF665/FFG665 package and 12 GTP I/O channels in the FF1136/FFG1136 package.
Number of GTP Transceiver I/O Channels/Device
Device
LX20TLX30T(1)SX35TLX50T(2)SX50T(3)LX85TSX95TLX110TLX155TLX220TSX240TLX330T
4444
4 or 84 or 84 or 84 or 8
8888
8 or 128 or 128 or 128 or 12
8 or 128 or 128 or 128 or 12
12121212
16161616
16161616
16161616
16161616
24242424
24242424
irtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)
August 9, 2024
Chapter 2:Pinout Tables
FF324 Package—LX30 and LX50
Table 2-2:FF324 Package—LX30 and LX50
Bank0000000
Pin Description
Pin Number
L10L9H10H9J10K9K10
No Connect (NC)
DXP_0DXN_0AVDD_0AVSS_0VP_0VN_0VREFP_0
Virtex-5 FPGA Packaging and Pinout Specification
FF1156 Package—TX150T
Table 2-7:FF1156 Package—TX150T (Continued)BankNANANANANANANANANANANANANANANANANANANANANANANANANANANANANANANANANA
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
Pin Description
Pin Number
M32M34N4N5N6N11N19N21N23N30N31P2P5P8P12P14P16P18P20P22P28P30P33R2R4R5R11R13R15R17R19R21R23
No Connect (NC)
Virtex-5 FPGA Packaging and Pinout Specification
FF1156 Package—TX150T
Table 2-7:FF1156 Package—TX150T (Continued)Bank27272727NANANANANANANANANANANANANANANANANANANANANANANANANANANANANA
VCCO_27VCCO_27VCCO_27VCCO_27VCCAUXVCCAUXVCCAUXVCCAUXVCCAUXVCCAUXVCCAUXVCCAUXVCCAUXVCCAUXVCCAUXVCCAUXVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINT
Pin Description
Pin Number
G24H21K25L22P23AB11T23M23N12N24P11R24T11U24V11Y11AA12AA14AA16AA18AA20AA22AB15AB17AB21AC18N14N18N20P13P15P17P19
No Connect (NC)
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 2:Pinout Tables
Table 2-10:
Bank3434343434343434NANANANANANANANANANANANANANANANANANANANANANANANANA
FF1760 Package—LX110, LX155, LX220, and LX330 (Continued)
Pin Description
Pin Number
BA27BB27AY27AY28BB29BB28BA29AY29E1K1R1Y1AE1AK1AR1AY1C2H2N2V2AC2AH2AN2AV2A3L3AA3AL3BA3D4P4AD4AP4
No Connect (NC)
IO_L16P_34 IO_L16N_34 IO_L17P_34 IO_L17N_34 IO_L18P_34 IO_L18N_34 IO_L19P_34 IO_L19N_34 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220
Virtex-5 FPGA Packaging and Pinout Specification
FPGA可编程逻辑器件芯片XC6VSX475T-2FFG1759C中文规格书 - 图文
