COMPILE ERROR DISPLAY CONTROLLING SYSTEM
申请(专利)号： JP19900218789
专利号： JPH04101229A 主分类号： G06F11/28
申请权利人： NEC CORP;
KOUBE NIHON DENKI
SOFUTOUEA KK 公开国代码： JP 优先权国家： JP
摘 要：
PURPOSE:To shorten the correcting time of a source program by displaying a line in which a compile error was caused and the contents of that error on a display screen as making them correspond to each other. CONSTITUTION:The source program is stored previously in a source program file 1, and is read in successively from the file 1 by source program read-in processing 2. Next, when the compile error is detected in syntax.meaning
analysis and interpretation processing, an error text generating means 5 outputs an error text 6, and this error text 6 is
constituted of a mark 31, the line number 32 of the source program in which the error was caused, and the contents 33 of the error. Namely, for instance, the error text 34 showing the error for the line whose line number is 19 is outputted to the source program, and similarly, the error text 35 showing the error for the line whose line number is 22 is outputted.
申请日： 1990-08-20 公开公告日： 1992-04-02
分类号： G06F11/28;
G06F9/45; G06F11/32 发明设计人： FUJIOKA
TOSHIYUKI; FUKUNISHI KAZUNORI 申请国代码： JP
优先权： 19900820 JP
21878990
摘 要 附 图：
Then, at last, the contents of the error are outputted to a display means 10 by an error text inserting means 8. Thus, the correcting time of the source program can be shortened. 主权项：
权 利 要 求 说 明 书
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COMPILE ERROR DISPLAY CONTROLLING SYSTEM
