Implementation
Overview
This chapter provides the information needed to map GTX_DUAL tiles instantiated in a design to device resources, including:???
The location of the GTX_DUAL tiles on the available device and packagecombinations.
The pad numbers of external signals associated with each GTX_DUAL tile.
How GTX_DUAL tiles and clocking resources instantiated in a design are mapped toavailable locations with a user constraints file (UCF).
It is a common practice to define the location of GTX transceivers early in the design
process to ensure correct usage of clock resources and to facilitate signal integrity analysis during board design. The implementation flow facilitates this practice through the use of location constraints in the UCF.
While this chapter describes how to instantiate GTX_DUAL clocking components, the details of the different GTX_DUAL tile clocking options are discussed in “Clocking,” page 96.
Ports and Attributes
Table4-1 shows the external ports associated with each GTX_DUAL tile.Table 4-1:
GTX_DUAL Tile External PortsPort
MGTTXP0MGTTXN0MGTTXP1MGTTXN1MGTRXP0MGTRXN0MGTRXP1MGTRXN1MGTREFCLKPMGTREFCLKNMGTAVCCPLL
InAnalog
N/AAnalog
Differential reference clock input pairPad for 1.0V supply for PLL
In
Embedded RX Clock
Differential receive data pairs for GTX transceivers 0 and 1
Out
Embedded TX Clock
Differential transmit data pairs for GTX transceivers 0 and 1
Dir
Domain
Description
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 4:Implementation
X-Ref Target - Figure 4-14Right Edge of the DieD16C16A14A15XCV5TX150T: Not AvailableXCV5TX240T: GTX_DUAL_X1Y11A17A16B13B14B18B17MGTREFCLKP_132MGTREFCLKN_132MGTRXP1_132MGTRXN1_132MGTRXP0_132MGTRXN0_132MGTTXP1_132MGTTXN1_132MGTTXP0_132MGTTXN0_132C14C15C17C13Power PinsMGTAVCCPLL_132MGTAVCC_132MGTAVTTRX_132MGTAVTTTX_132D10C10A8A9XCV5TX150T: GTX_DUAL_X1Y9XCV5TX240T: GTX_DUAL_X1Y10A11A10B7B8B12B11MGTREFCLKP_128MGTREFCLKN_128MGTRXP1_128MGTRXN1_128MGTRXP0_128MGTRXN0_128MGTTXP1_128MGTTXN1_128MGTTXP0_128MGTTXN0_128C8C9C11C7MGTAVCCPLL_128MGTAVCC_128MGTAVTTRX_128MGTAVTTTX_128C4C3A2A3XCV5TX150T: GTX_DUAL_X1Y8XCV5TX240T: GTX_DUAL_X1Y9A5A4B1B2B6B5MGTREFCLKP_124MGTREFCLKN_124MGTRXP1_124MGTRXN1_124MGTRXP0_124MGTRXN0_124MGTTXP1_124MGTTXN1_124MGTTXP0_124MGTTXN0_124C2D4C5C1MGTAVCCPLL_124MGTAVCC_124MGTAVTTRX_124MGTAVTTTX_124F4F3H1G1XCV5TX150T: GTX_DUAL_X1Y7XCV5TX240T: GTX_DUAL_X1Y8E1F1J2H2D2E2MGTREFCLKP_120MGTREFCLKN_120MGTRXP1_120MGTRXN1_120MGTRXP0_120MGTRXN0_120MGTTXP1_120MGTTXN1_120MGTTXP0_120MGTTXN0_120H3G3E3J3MGTAVCCPLL_120MGTAVCC_120MGTAVTTRX_120MGTAVTTTX_120UG198_c4_17_090508Figure 4-14:XC5VTX150T-FF1759 and XC5VTX240T-FF1759 GTX Placement (1 of 6)
RocketIO GTX Transceiver User Guide
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Package Placement Information
X-Ref Target - Figure 4-19Power PinsMGTAVCCPLL_121MGTAVCC_121MGTAVTTRX_121MGTAVTTTX_121AV40AU40AR40AW40MGTREFCLKP_121MGTREFCLKN_121MGTRXP1_121MGTRXN1_121MGTRXP0_121MGTRXN0_121MGTTXP1_121MGTTXN1_121MGTTXP0_121MGTTXN0_121Left Edge of the DieAT39AT40AV42AU42AR42AT42AW41AV41AP41AR41XCV5TX150T: GTX_DUAL_X0Y2XCV5TX240T: GTX_DUAL_X0Y3MGTAVCCPLL_125MGTAVCC_125MGTAVTTRX_125MGTAVTTTX_125AY38AW38AY41AY37MGTREFCLKP_125MGTREFCLKN_125MGTRXP1_125MGTRXN1_125MGTRXP0_125MGTRXN0_125MGTTXP1_125MGTTXN1_125MGTTXP0_125MGTTXN0_125AW39AY39BB38BB39BB41BB40BA37BA38BA42BA41XCV5TX150T: GTX_DUAL_X0Y1XCV5TX240T: GTX_DUAL_X0Y2MGTAVCCPLL_129MGTAVCC_129MGTAVTTRX_129MGTAVTTTX_129AY32AY33AY35AY31MGTREFCLKP_129MGTREFCLKN_129MGTRXP1_129MGTRXN1_129MGTRXP0_129MGTRXN0_129MGTTXP1_129MGTTXN1_129MGTTXP0_129MGTTXN0_129AW34AY34BB32BB33BB35BB34BA31BA32PA36BA35XCV5TX150T: GTX_DUAL_X0Y0XCV5TX240T: GTX_DUAL_X0Y1MGTAVCCPLL_133MGTAVCC_133MGTAVTTRX_133MGTAVTTTX_133AY26AY27AY29AY25MGTREFCLKP_133MGTREFCLKN_133MGTRXP1_133MGTRXN1_133MGTRXP0_133MGTRXN0_133MGTTXP1_133MGTTXN1_133MGTTXP0_133MGTTXN0_133AW28AY28BB26BB27BB29BB28BA25BA26BA30BA29UG198_c4_16_071008XCV5TX150T: Not AvailableXCV5TX240T: GTX_DUAL_X0Y0Figure 4-19:XC5VTX150T-FF1759 and XC5VTX240T-FF1759 GTX Placement (6 of 6)
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 5:Tile Features
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 5:Tile Features
X-Ref Target - Figure 5-7GTX_DUAL RESET After ConfigurationGTX0RXCDRRESET0RXRESET0TXRESET0TXRESET1GTX1RXCDRRESET1RXRESET1RXBUFRESET0RXBUFRESET1UG198_c5_07_052107Figure 5-7:GTX_DUAL Reset Hierarchy
Ports and Attributes
Table5-6 defines the shared tile reset ports.
Table 5-6:
Shared Tile Reset PortsPort
Dir
Domain
Description
This port is driven High and then deasserted to start the full GTX_DUAL reset sequence. This sequence takes about 120μs to complete, and systematically resets all subcomponents of the GTX_DUAL tile.
This port goes High when the GTX transceiver has finished reset and is ready for use. For this signal to work correctly, CLKIN and all clock inputs on the individual GTX transceiver (TXUSRCLK, TXUSRCLK2, RXUSRCLK, RXUSRCLK2) must be driven.This active-High signal resets the RX elastic buffer logic.
GTXRESET(1)(2)
InAsync
RESETDONE0 RESETDONE1RXBUFRESET0(1)RXBUFRESET1(2)RXCDRRESET0(1)RXCDRRESET1(2)RXRESET0(1)RXRESET1(2)TXRESET0(1)TXRESET1(2)
Notes:
OutAsync
InAsync
In
Individual reset signal for the RX CDR and the RX part of the PCS
RXUSRCLK2for this channel. This signal is driven High to cause the CDR to give
up its current lock and return to the shared PMA PLL frequency.
AsyncAsync
Active-High reset for the RX PCS logic.
Resets the PCS of the GTX transmitter, including the phase adjust FIFO, the 8B/10B encoder, and the FPGA TX interface.
InIn
1.When these resets are active, then RESETDONE0 is driven Low. All resets are asynchronous, positive-edge triggered, andsynchronized internally to a specific clock domain.
2.When these resets are active, then RESETDONE1 is driven Low. All resets are asynchronous, positive-edge triggered, andsynchronized internally to a specific clock domain.
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FPGA可编程逻辑器件芯片XC6VLX75T-2FFG484C中文规格书 - 图文
