FPGA可编程逻辑器件芯片EP1SGX25DF672C7N中文规格书

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The memory address depths and output widths can be configured as 4,096×1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256×18bits), and 128 × 32 (or 128 × 36 bits). The 128×32- or 36-bit configuration is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths. Tables25 and 26 summarize the possible M4K RAM block configurations.

Table25.M4K RAM Block Configurations (Simple Dual-Port)Read Port

4K × 12K × 21K × 4512 × 8256 × 16128 × 32512 × 9256 × 18128 × 36

Write Port

4K 1vvvvvv

2K × 2vvvvvv

1K ° 4512 ° 8vvvvvv

vvvvvv

256 ° 16vvvvvv

128 ° 32vvvvvv

vvv

512 °9

256 ° 18

128 ° 36

Table26.M4K RAM Block Configurations (True Dual-Port)

Port A

4K × 12K × 21K × 4512 × 8256 × 16512 × 9256 × 18

Port B

4K × 1vvvvv

2K × 2vvvvv

1K × 4vvvvv

512 × 8vvvvv

256 × 16vvvvv

512 × 9

256 × 18

When the M4K RAM block is configured as a shift register block, the

designer can create a shift register up to 4,608 bits (w×m×n).

StratixGX FPGA Family

Table36.Multiplier Size & Configurations per DSP block

DSP Block Mode

Multiplier

Multiply-accumulatorTwo-multipliers adderFour-multipliers adder

9 × 9

Eight multipliers with eight product outputsTwo multiply and accumulate (52 bits)Four sums of two

multiplier products eachTwo sums of four

multiplier products each

18 × 1836 × 36 (1)

Four multipliers with four One multiplier with one product outputsproduct outputTwo multiply and accumulate (52 bits)Two sums of two

multiplier products each

– –

One sum of four multiplier –products each

PLLs & Clock Networks

Figure89.Regional Clock Bus

Clocks Availableto a Quadrantor Half-Quadrant Global Clock Network [15..0]Regional Clock Network [3..0]Fast Regional Clock Network [1..0]Horizontal I/OCell IO_CLK[7..0]Clock [21:0]Lab Row Clock [7..0]Vertical I/O CellIO_CLK[7..0]PLLs & Clock Networks

Any of the four external output counters can drive the single-ended or differential clock outputs for PLLs 5 and 6. This means one counter or frequency can drive all output pins available from PLL 5 or PLL6. Each pair of output pins (four pins total) has dedicated VCC and GND pins to reduce the output clock’s overall jitter by providing improved isolation from switching I/O pins.

For PLLs 5 and 6, each pin of a single-ended output pair can either be in phase or 180° out of phase. The clock output pin pairs support the same I/O standards as standard output pins (in the top and bottom banks) as well as LVDS, LVPECL, 3.3-V PCML, HyperTransport technology, differential HSTL, and differential SSTL. Table40 shows which I/O

standards the enhanced PLL clock pins support. When in single-ended or differential mode, the two outputs operate off the same power supply. Both outputs use the same standards in single-ended mode to maintain performance. Designers can also use the external clock output pins as user output pins if external enhanced PLL clocking is not needed.

Table40.I/O Standards Supported for Enhanced PLL Pins(Part 1 of2)

I/O Standard

LVTTLLVCMOS2.5 V1.8 V1.5 V3.3-V PCI3.3-V PCI-XLVPECL3.3-V PCMLLVDS

HyperTransport technologyDifferential HSTL Differential SSTL 3.3-V GTL3.3-V GTL+1.5-V HSTL class I1.5-V HSTL class IISSTL-18 class ISSTL-18 class II

vvvvvv

Input

INCLK

vvvvvvvvvvvv

Output

PLLENABLE

FBIN

vvvvvvvvvvv