WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
申请(专利)号： US201916523573
专利号： US2020043841A1 主分类号： H01L23/498 申请权利人： SHINKO
ELECTRIC
INDUSTRIES CO., LTD. 公开国代码： US 优先权国家： JP
摘 要：
A wiring substrate includes first wiring portions, an insulation layer covering the first wiring portions, openings extending through the insulation layer in a thickness-wise direction, partially
exposing upper surfaces of the first wiring portions, and differing from each other in capacity, and second wiring portions, each of which includes a via wiring filling one of the openings and a columnar
connection terminal electrically connected to the via wiring and arranged on an
upper surface of the insulation layer. The via wiring includes an electrolytic plated layer and an electroless plating structure including N layers (N is integer and ≥0) arranged between the electrolytic plated layer and the upper surface of the first wiring portion exposed in a bottom of the opening. The via wiring is formed so that the electroless plating structure has a thickness that increases as a capacity of the opening filled with the via wiring is
申请日： 2019-07-26 公开公告日： 2020-02-06
分类号： H01L23/498;
H01L21/48 发明设计人： TAKASHI ARAI;
FUMIMASA KATAGIRI;
KATSUYA FUKASE 申请国代码： US
优先权： 20180731 JP 2018-143361
摘 要 附 图：
increased. 主权项：
1. A wiring substrate, comprising:
权 利 要 求 说 明 书
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WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
