Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table58 and Table59) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Table60 through Table63) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Table58 and Table59.
Period jitter and cycle-cycle jitter are two (of many) different ways of characterizing clock jitter. Both specifications describe statistical variation from a mean value.
Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods sampled (usually from 100,000 to more than a million samples for specification purposes). In a histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero.
Delay-Locked Loop (DLL)
Table 58:Recommended Operating Conditions for the DLL
Speed Grade
Symbol
Input Frequency RangesFCLKIN
CLKIN_FREQ_DLL_LFCLKIN_FREQ_DLL_HF
Input Pulse RequirementsCLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN period
FCLKIN ≤ 100 MHzFCLKIN > 100 MHz
LowHighAllAll
40E%––––
Allowable variation of off-chip feedback delay from the DCM output to the CLKFB input
–
60U%
40E%–––––
60U%
--pspsnsns
Frequency for the CLKIN input
LowHigh
18(2)48
167(3)280(3)
18(2)48
167(3)280(3)(4)
MHzMHz
Description
Frequency Mode/FCLKIN Range
Min
-5Max
Min
-4Max
Units
Input Clock Jitter Tolerance and Delay Path Variation(5)CLKIN_CYC_JITT_DLL_LFCLKIN_CYC_JITT_DLL_HFCLKIN_PER_JITT_DLL_LF CLKIN_PER_JITT_DLL_HF CLKFB_DELAY_VAR_EXT
Cycle-to-cycle jitter at the CLKIN input
Period jitter at the CLKIN input
±300±150±1±1
±300±150±1±1
Notes:
1.DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2.3.4.5.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table60.
The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to FBUFG. When set to TRUE,CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM.
Industrial temperature range devices have additional requirements for continuous clocking, as specified in Table64.CLKIN input jitter beyond these limits may cause the DCM to lose lock. See UG331 for more details.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
Table 100:FG456 Package Pinout (Cont’d)
Bank2222222222222222222222222222222222223333
3S400 Pin Name
IO_L21P_2IO_L22N_2IO_L22P_2
IO_L23N_2/VREF_2IO_L23P_2IO_L24N_2IO_L24P_2N.C. (?)N.C. (?)IO_L27N_2IO_L27P_2N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)
IO_L34N_2/VREF_2IO_L34P_2IO_L35N_2IO_L35P_2IO_L38N_2IO_L38P_2IO_L39N_2IO_L39P_2IO_L40N_2IO_L40P_2/VREF_2VCCO_2VCCO_2VCCO_2VCCO_2VCCO_2IO
IO_L01N_3/VRP_3IO_L01P_3/VRN_3IO_L16N_3
3S1000, 3S1500, 3S2000FG456
Pin NamePin NumberIO_L21P_2IO_L22N_2IO_L22P_2
IO_L23N_2/VREF_2IO_L23P_2IO_L24N_2IO_L24P_2IO_L26N_2IO_L26P_2IO_L27N_2IO_L27P_2IO_L28N_2IO_L28P_2IO_L29N_2IO_L29P_2IO_L31N_2IO_L31P_2IO_L32N_2IO_L32P_2IO_L33N_2IO_L33P_2
IO_L34N_2/VREF_2IO_L34P_2IO_L35N_2IO_L35P_2IO_L38N_2IO_L38P_2IO_L39N_2IO_L39P_2IO_L40N_2IO_L40P_2/VREF_2VCCO_2VCCO_2VCCO_2VCCO_2VCCO_2IO
IO_L01N_3/VRP_3IO_L01P_3/VRN_3IO_L16N_3
E22G17G18F19G19F20F21G20H19G21G22H18J17H21H22J18J19J21J22K17K18K19K20K21K22L17L18L19L20L21L22H17H20J16K16L16Y21Y20Y19W22
TypeI/OI/OI/OVREFI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OVREFI/OI/OI/OI/OI/OI/OI/OI/OVREFVCCOVCCOVCCOVCCOVCCOI/ODCIDCII/O
DS099 (v3.1) June 27, 2013
Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
Table 100:FG456 Package Pinout (Cont’d)
Bank3333333333333333333333333333333333333333
3S400 Pin Name
IO_L16P_3IO_L17N_3IO_L17P_3/VREF_3IO_L19N_3IO_L19P_3IO_L20N_3IO_L20P_3IO_L21N_3IO_L21P_3IO_L22N_3IO_L22P_3IO_L23N_3IO_L23P_3/VREF_3IO_L24N_3IO_L24P_3N.C. (?)N.C. (?)IO_L27N_3IO_L27P_3N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)N.C. (?)IO_L34N_3IO_L34P_3/VREF_3IO_L35N_3IO_L35P_3IO_L38N_3IO_L38P_3IO_L39N_3IO_L39P_3
IO_L40N_3/VREF_3IO_L40P_3VCCO_3
3S1000, 3S1500, 3S2000FG456
Pin NamePin NumberIO_L16P_3IO_L17N_3IO_L17P_3/VREF_3IO_L19N_3IO_L19P_3IO_L20N_3IO_L20P_3IO_L21N_3IO_L21P_3IO_L22N_3IO_L22P_3IO_L23N_3IO_L23P_3/VREF_3IO_L24N_3IO_L24P_3IO_L26N_3IO_L26P_3IO_L27N_3IO_L27P_3IO_L28N_3IO_L28P_3IO_L29N_3IO_L29P_3IO_L31N_3IO_L31P_3IO_L32N_3IO_L32P_3IO_L33N_3IO_L33P_3IO_L34N_3IO_L34P_3/VREF_3IO_L35N_3IO_L35P_3IO_L38N_3IO_L38P_3IO_L39N_3IO_L39P_3
IO_L40N_3/VREF_3IO_L40P_3VCCO_3
Y22V19W19W21W20U19V20V22V21T17U18U21U20R18T18T20T19T22T21R22R21P19R19P18P17P22P21N18N17N20N19N22N21M18M17M20M19M22M21M16
TypeI/OI/OVREFI/OI/OI/OI/OI/OI/OI/OI/OI/OVREFI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OVREFI/OI/OI/OI/OI/OI/OVREFI/OVCCO
DS099 (v3.1) June 27, 2013
Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
I/O Bank01234567
EdgeTopRightBottomLeft
Maximum I/O
3535313135353131
All Possible I/O Pins by Type
I/O2727252521212525
DUAL00006600
DCI22222222
VREF44444444
GCLK22002200
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
FG456 Footprint
Left Half of FG456 Package (Top View)
XC3S400
(264 max. user I/O)196I/O: Unrestricted,
general-purpose user I/O32
VREF: User I/O or input voltage reference for bankN.C.: Unconnected pins for XC3S400 (?)
X-Ref Target - Figure 511ABGND2PROG_B3456Bank 078910I/O11I/O L32P_0 GCLK6I/O I/O IO I/O I/O I/O I/O L19P_0 VCCAUXVREF_0L01P_0 L24P_0L27P_0L09P_0VRN_0?I/O I/O ?TDII/O GNDHSWAP_I/O I/O L19N_0I/O I/O I/O L01N_0L32N_0ENL09N_0L15P_0L24N_0L27N_0L29P_0VRP_0GCLK7CL16P_7 I/OVREF_7I/O I/O I/O I/O IOL01N_7L01P_7 VREF_0VCCO_0L06P_0L15N_0VRP_7VRN_7GNDI/O I/O L31P_0 L29N_0VREF_0I/OI/O L31N_0I/O I/O I/O I/O I/O I/O I/O I/O L22P_0 I/ODL16N_7L19P_7L19N_7L17P_7L06N_0L10P_0L16P_0VREF_7?IO I/O 69
I/O I/O I/O I/O I/O I/O I/O VREF_0 I/O I/O L22N_0 EL21N_7L21P_7L20P_7L17N_7L10N_0L16N_0L25P_0L28P_0L30P_0??Bank 7XC3S1000, XC3S1500,
XC3S2000 (333 max user I/O)
I/O: Unrestricted, 261
general-purpose user I/O36
VREF: User I/O or input voltage reference for bankN.C.: No unconnected pins in this package
FVCCAUXI/O I/O I/O I/O L23N_7L23P_7L20N_7L22P_7I/O I/O I/O I/OIO I/O I/O I/O VREF_0VCCO_0L25N_0L28N_0L30N_0VCCO_0VCCO_0VCCO_0I/O I/O I/O VCCINTVCCINTL27P_7 L26N_7L26P_7 GL27N_7L24P_7L22N_7VREF_7?? L28P_7 VCCO_7L29P_7 I/O VCCO_7VCCINTHL28N_7L24N_7??I/O I/O JL32N_7L32P_7 GND???I/O I/O I/O L29N_7L31N_7L31P_7 VCCO_7???I/O I/O I/O 0
GNDGNDGNDAll devices
DUAL: Configuration pin, 12then possible user I/O8
GCLK: User I/O or global clock buffer input
DCI: User I/O or reference resistor input for bankCONFIG: Dedicated configuration pinsJTAG: Dedicated JTAG port pins
I/O I/O I/O I/O I/O I/O L33N_7L33P_7 VCCO_7KL35N_7L35P_7L34N_7L34P_7??I/O I/O I/O I/O I/O VCCO_7LL40N_7L40P_7L39N_7L39P_7L38N_7L38P_7VREF_7I/O I/O I/O I/O I/O VCCO_6ML40P_6 L40N_6L39P_6L39N_6L38P_6L38N_6VREF_6I/O I/O I/O I/O I/O I/O L33N_6 VCCO_6NL35P_6L35N_6L34P_6L34N_6L33P_6 VREF_6??L32N_6PL32P_6 ??I/O I/O I/O I/O GNDI/O I/O I/O L31P_6 L31N_6L28P_6 VCCO_6???I/O ?I/O ?I/O I/O GNDGNDGNDGNDGNDGNDGNDGNDGND16
GNDGNDGND7
GNDGNDGND4
L29N_6RL29P_6 ??L28N_6VCCO_6VCCINTVCCO_6L26P_6 Bank 612
VCCINT: Internal core
voltage supply (+1.2V)VCCO: Output voltage supply for bank
VCCAUX: Auxiliary voltage supply (+2.5V)GND: Ground
I/O I/O I/O L26N_6I/O I/O I/O VCCINTVCCINTVCCO_5VCCO_5VCCO_5TL27P_6L27N_6L23P_6L22P_6L22N_6?40UVCCAUXI/O I/O I/O I/O IOI/OL24N_6L24P_6VREF_6L23N_6L19P_6VREF_5VCCO_5I/O ?I/OI/OI/O L31P_5 D58
I/O I/O I/O I/O I/O I/O I/OVL21P_6L21N_6L20P_6L20N_6L19N_6L15P_5I/O I/O L24P_5L27P_5I/O52
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O L19P_5 I/O L27N_5L29P_5 L31N_5 WL17P_6 VREF_5L24N_5VREF_6L17N_6L16P_6L16N_6L09P_5L15N_5VREF_5VREF_5D4?YAAABI/OI/O I/O I/O I/O I/O I/O L19N_5VCCO_5L01P_6 L01N_6L01N_5VRN_6VRP_6RDWR_BL09N_5L16P_5?GNDGNDI/O I/O L32P_5 L29N_5GCLK2M1I/O I/O I/O I/O I/O I/O I/O L22P_5 I/O I/O L01P_5 L10P_5 L28P_5 L32N_5L25P_5CS_BL06P_5VRN_5L16N_5D7L30P_5GCLK3?M2I/O I/O I/O I/O I/O I/O IOL22N_5 VCCAUXL10N_5 L28N_5VREF_5L06N_5VRP_5L25N_5L30N_5D6?GNDM0Bank 5DS099-4_11a_030203Figure 51:FG456 Package Footprint (Top View)DS099 (v3.1) June 27, 2013
Product Specification
FPGA可编程逻辑器件芯片XC6VSX315T-1FFG1156C中文规格书 - 图文
