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Chapter 2:Logic Array Blocks and Adaptive Logic Modules in StratixIII Devices

Adaptive Logic Modules

Each ALM has two sets of outputs that drive the local, row, and column routing resources. The LUT, adder, or register output can drive these output drivers (refer to Figure2–6). For each set of output drivers, two ALM outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also drive local interconnect resources. This allows the LUT or adder to drive one output while the register drives another output.

This feature, called register packing, improves device utilization because the device can use the register and the combinational logic for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same ALM so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The ALM can also drive out registered and unregistered versions of the LUT or adder output.

ALM Operating Modes

The StratixIII ALM can operate in one of the following modes:

■■■■■

Normal

Extended LUT ModeArithmeticShared ArithmeticLUT-Register

Each mode uses ALM resources differently. In each mode, eleven available inputs to an ALM—the eight data inputs from the LAB local interconnect, carry-in from the previous ALM or LAB, the shared arithmetic chain connection from the previous ALM or LAB, and the register chain connection—are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock,

asynchronous clear, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all ALM modes. 1

Refer to “LAB Control Signals” on page2–4 for more information on the LAB-wide control signals.

The QuartusII software and supported third-party synthesis tools, in conjunction with parameterized functions such as the library of parameterized modules (LPM) functions, automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions.

Normal Mode

The normal mode is suitable for general logic applications and combinational

functions. In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. The normal mode allows two functions to be

implemented in one StratixIII ALM, or an ALM to implement a single function of up to six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs. Figure2–7 shows the supported LUT combinations in normal mode.

Stratix III Device Handbook, Volume 1

Chapter 1:StratixIII Device Family Overview

Chapter Revision History

Stratix III Device Handbook, Volume 1

2.Logic Array Blocks and Adaptive Logic

Modules in StratixIII Devices

SIII51002-1.5

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Chapter 2:Logic Array Blocks and Adaptive Logic Modules in StratixIII DevicesAdaptive Logic Modules

Figure2–4.LAB-Wide Control Signals

There are two uniqueclock signals per LAB.Dedicated Row LAB Clocks666Local InterconnectLocal InterconnectLocal InterconnectLocal InterconnectLocal InterconnectLocal Interconnectlabclk0labclkena0or asyncloador labpresetlabclk1labclkena1labclk2labclkena2syncloadlabclr0labclr1synclrAdaptive Logic Modules

The basic building block of logic in the StratixIII architecture, the adaptive logic

module (ALM), provides advanced features with efficient logic utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided between two combinational adaptive LUTs (ALUTs) and two registers. With up to eight inputs to the two combinational ALUTs, one ALM can implement various combinations of two functions. This adaptability allows an ALM to be completely backward-compatible with four-input LUT architectures. One ALM can also implement any function of up to six inputs and certain seven-input functions.

In addition to the adaptive LUT-based resources, each ALM contains two

programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain. Through these dedicated resources, an ALM can efficiently implement various arithmetic functions and shift registers. Each ALM drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects. Figure2–5 shows a high-level block diagram of the StratixIII ALM while Figure2–6 shows a detailed view of all the connections in an ALM.

Stratix III Device Handbook, Volume 1

Chapter 2:Logic Array Blocks and Adaptive Logic Modules in StratixIII DevicesAdaptive Logic Modules

Figure2–13.ALM in Shared Arithmetic Mode

shared_arith_in

carry_inlabclk4-InputLUTDQTo general orlocal routingTo general orlocal routing

datae0datacdatabdataa

4-InputLUTreg0dataddatae1

4-InputLUTDQTo general orlocal routingTo general orlocal routing

4-InputLUTreg1carry_outshared_arith_out

You can find adder trees in many different applications. For example, the summation of the partial products in a logic-based multiplier can be implemented in a tree

structure. Another example is a correlator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or to de-spread data that was transmitted utilizing spread spectrum technology.

An example of a three-bit add operation utilizing the shared arithmetic mode is shown in Figure2–14. The partial sum (S[3..0]) and the partial carry (C[3..0]) is obtained using the LUTs, while the result (R[3..0]) is computed using the dedicated adders.

Stratix III Device Handbook, Volume 1