Master BPI Configuration Interface
Determining the Maximum Configuration Clock Frequency
In Master BPI mode, the FPGA delivers the configuration clock. The master configuration clock frequency of the FPGA is set through the BitGen -g ConfigRate option. The BitGen -g ConfigRate option sets the nominal configuration clock frequency. The default BitGen ConfigRate setting of 2 is recommended. This default value sets the
nominal master CCLK frequency to 2MHz, which satisfies timing requirements for the leading BPI flash families. If the timing requirements discussed in this section are satisfied, the BitGen ConfigRate setting can be increased for a faster configuration time. When determining a valid ConfigRate setting, these timing parameters must be considered:?????
FPGA nominal master CCLK frequency (BitGen ConfigRate)FPGA Master CCLK frequency tolerance (FMCCKTOL)A[25:0] outputs valid after CCLK falling edge (TBPICCO)BPI flash address to output valid (access) time (TACC)FPGA data setup time to CCLK rising edge (TBPIDCC)
The master configuration clock of the FPGA has a tolerance of FMCCKTOL. Due to the master configuration clock tolerance (FMCCKTOL), the BitGen -g ConfigRate option must be checked so that half the period for the worst-case (fastest) master CCLK frequency is greater than the sum of the FPGA address valid time, BPI flash access time, and FPGA set up time, as shown in Equation2-1.
1
------------------------------------------------------------------------------------------------≥TBPICCO+TACC+TBPIDCCEquation2-1
2×ConfigRate×FMCCKTOLMAX
Power-On Sequence Precautions
At power-on, the FPGA automatically starts its configuration procedure. When the FPGA is in a Master-BPI configuration mode, the FPGA asserts FCS_B Low and drives a sequence of addresses to read the bitstream from a parallel NOR flash. The parallel NOR flash must be ready for asynchronous reads before the FPGA drives FCS_B Low and outputs the first address to ensure the parallel NOR flash can output the stored bitstream.
Because different power rails can supply the FPGA and parallel NOR flash or because the FPGA and parallel NOR flash can respond at different times along the ramp of a shared power supply, special attention to the FPGA and parallel NOR flash power-on sequence or power-on ramps is essential. The power-on sequence or power supply ramps can cause the FPGA to awake before the parallel NOR flash or vice versa. For many systems with near-simultaneous power supply ramps, the FPGA power-on reset time (TPOR) can sufficiently delay the start of the FPGA configuration procedure such that the parallel NOR flash becomes ready before the start of the FPGA configuration procedure. In general, the system design must consider the effect of the power sequence, the power ramps, FPGA power-on reset time, and parallel NOR flash power-on reset time on the timing relation between the start of FPGA configuration and the readiness of the parallel NOR flash for asynchronous reads. Check DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics, for Spartan-6 FPGA power supply requirements and timing.
One of the following system design approaches can ensure that the parallel NOR flash is ready for asynchronous reads before the FPGA starts its configuration procedure:?
Control the sequence of the power supplies such that the parallel NOR flash is certainto be powered and ready for asynchronous reads before the FPGA begins itsconfiguration procedure.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
Chapter 2:Configuration Interface Basics
?
Hold the FPGA PROGRAM_B pin Low from power-up to delay the start of the FPGAconfiguration procedure and release the PROGRAM_B pin to High after the parallelNOR flash is fully powered and is able to perform asynchronous reads.
Hold the FPGA INIT_B pin Low from power-up to delay the start of the FPGAconfiguration procedure and release the INIT_B pin to High after the parallel NORflash becomes ready for asynchronous reads.
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External Configuration Clock for Master Modes
By default, Spartan-6 FPGAs perform master mode configuration using an internally generated clock source. However, Spartan-6 FPGAs support the ability to dynamically switch to an external clock source during master mode configuration. The external clock source is effective for an application where faster and stable configuration times are needed.
Table 2-8:Spartan-6 FPGA External Configuration Clock Interface Pin
Pin NameUSERCCLK
Type
Input
Dedicated or Dual-Purpose
Dual-purpose
Description External
configuration clock source for all master configuration modes
USERCCLK is a dual-purpose pin that can be used by the application as GCLK0 after the configuration. To enable the external clock source during master mode configuration, the ExtMasterCclk_en option in BitGen must be enabled. The USERCCLK frequency can be divided down using the ExtMasterCclk_divide BitGen option. The allowable values are 1 (default) and all even numbers between 2 and 1022. The I/O standard for the
USERCCLK is LVCMOS 8mA slow slew rate. The configuration begins with the CCLK generated by the FPGA internal oscillator. When the configuration clock register setting is reached in the bitstream, the FPGA switches from the internal oscillator to the clock found on USERCCLK (or divided down, as set by the BitGen option ExtMasterCclk_divide). The clock multiplexer is designed to generate a glitchless output clock during the
transition. Care must be exercised when also using this clock output as an input to the design. When the end of startup (EOS) completes, the I/O standard for this pin as specified by the design is enabled. At this time, the input of this pin might glitch as the I/O changes from the default I/O standard to the user-specified I/O standard.
Board Layout for Configuration Clock (CCLK)
The Spartan-6 FPGA configuration I/Os use the LVCMOS slow slew rate 8mA I/O standard. This requires more attention to PCB trace routing and termination for proper signal integrity.
These basic guidelines must be followed:???
Route the CCLK net as a 50Ω controlled impedance transmission line.Always route the CCLK net without any branching; do not use a star topology(Figure2-25).
Stubs, if necessary, must be shorter than 8mm (0.3 inches).
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2024
Boundary-Scan for Spartan-6 Devices Using IEEE Std 1149.1
Using Boundary-Scan in Spartan-6 Devices
For single-device configuration, the TAP controller commands are issued automatically if the part is being configured with Xilinx? iMPACT software. The download cable must be attached to the appropriate four JTAG pins (TMS, TCK, TDI, and TDO) to deliver the bitstream automatically from the computer port to the Spartan-6 FPGA. The iMPACT software automatically checks for proper connections and drives the commands to deliver and/or verify that the configuration bits are properly managed.
Figure3-2 shows a typical JTAG setup with the simple connection required to attach a single device to a JTAG signal header, which can be driven from a processor or a Xilinx programming cable under control of iMPACT software. TCK is the clock used for
boundary-scan operations. The TDO-TDI connections create a serial datapath for shifting data through the JTAG chain. TMS controls the transition between states in the TAP
controller; see Chapter10, Advanced JTAG Configurations. Proper physical connections of all of these signals are essential to JTAG functionality.
X-Ref Target - Figure 3-2JTAG HeaderSpartan-6 FPGATDOTDITMSTCKTDITMSTCKDeviceUG380_c3_02_042909TDOFigure 3-2:Single-Device JTAG Programming Connections
Multiple Device Configuration
It is possible to configure multiple Spartan-6 devices in a chain. (See Figure3-3.)
X-Ref Target - Figure 3-3JTAG HeaderTDOSpartan-6FPGATDITMSTCKTDITMSTCKPROGRAM_BTDOSpartan-6FPGATDITMSTCKPROGRAM_BTDOSpartan-6FPGATDITMSTCKPROGRAM_BTDODevice 0Device 1Device 2UG380_c3_03_042909Figure 3-3:Boundary-Scan Chain of Devices
If JTAG is the only configuration mode, then PROGRAM_B, INIT_B, and DONE can be tied High to a 330Ω resistor.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
POST_CRC_INTERNAL
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
Chapter 4:User Primitives
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2024
FPGA可编程逻辑器件芯片XC2S150-6FGG256I中文规格书 - 图文
