Chapter 6:GTX Transmitter (TX)
TX PRBS Generator
Overview
Pseudo-random bit sequences (PRBS) are commonly used to test the signal integrity of high-speed links. These sequences appear random but have specific properties that can be used to measure the quality of a link.
The GTX PRBS block can generate several industry-standard PRBS patterns. Table6-13 lists the available PRBS patterns and their typical uses.
Table 6-13:NamePRBS-7PRBS-23
Pseudo-Random Bit SequencesPolynomial1+X6+X7 (inverted)1+X18+X23 (inverted)1+X28+X31 (inverted)
Length of Consecutive Sequence (bits)Zeros
27–1223–1
723
Typical Use
Used to test channels with 8B/10B.
ITU-T Recommendation O.150, Section 5.6. One of the
recommended test patterns in the SONET specification.ITU-T Recommendation O.150, Section 5.8. A recommended PRBS test pattern for 10 Gigabit Ethernet. See IEEE 802.3ae-2002.
PRBS-31
231
–131
Ports and Attributes
Table6-14 defines the TX PRBS generator ports.
Table 6-14:
TX PRBS Generator Ports
Direction
Clock Domain
Description
Transmitter test pattern generation control. A pseudo-random bit sequence (PRBS) is generated by enabling the test pattern generation circuit.
TXENPRBSTST0[1:0]TXENPRBSTST1[1:0]
00: Test pattern generation off (standard operation mode)
In
TXUSRCLK2
01: Enable 27–1 PRBS generation10: Enable 223–1 PRBS generation11: Enable 231–1 PRBS generation
Because PRBS patterns are deterministic, the receiver can check the received data against a sequence of its own PRBS generator.
Port
There are no attributes in this section.
Description
Each GTX transceiver includes a built-in PRBS generator. This feature can be used in
conjunction with other test features, such as loopback and the built-in PRBS checker, to run tests on a given channel.
To use the PRBS generator, the PRBS test mode is selected using the TXENPRBSTST port. Table6-14 lists the available settings.
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 6:GTX Transmitter (TX)
Figure6-24 illustrates the rise times associated with the receiver present and receiver absent conditions, along with the detection threshold.
X-Ref Target - Figure 6-24τ? RTERMCCH < 180 nsVDDrcvRefReceiver AbsentReceiver PresentVDD – VSWING/2τ? 1/2RTERMCCHrcvDlyτ? 2RTERMCAC > 6000 nsTimeUG198_c6_24_101207Figure 6-24:Receive Detection Thresholds
When the PHY has completed the receiver detect sequence, it asserts PHYSTATUS for one clock and drives the RXSTATUS signals to the appropriate code. After the receiver
detection is completed (as signaled by the assertion of PHYSTATUS), TXDETECTRX must be deasserted. Figure6-25 shows this process.
X-Ref Target - Figure 6-25TXUSRCLK2TXDETECTRXRXPOWERDOWN[1:0]TXPOWERDOWN[1:0]10bPHYSTATUSRXUSRCLK2RXSTATUS[2:0]000bStatusUG198_c6_25_101207Figure 6-25:Receiver Detect Waveforms
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
TX Out-of-Band/Beacon Signaling
TX Out-of-Band/Beacon Signaling
Overview
Each GTX transceiver provides support for generating the Out-of-Band (OOB) sequences described in the Serial ATA (SATA) specification and beaconing described in the PCI
Express specification. See AppendixB, “OOB/Beacon Signaling,” for an overview of OOB signaling and how it is used in these protocols.
GTX_DUAL support for SATA OOB signaling consists of the analog circuitry required to encode the OOB signal state and state machines to format bursts of OOB signals for SATA COM sequences (COMRESET, COMWAKE, and COMINIT). Each GTX transceiver also supports SATA auto-negotiation by allowing the timing of the COM sequences to be changed based on the divider settings used for the TX line rate.
GTX_DUAL supports beaconing as described in the PHY Interface for the PCI Express (PIPE) Specification. The format of the beacon sequence is controlled by the FPGA logic.
Ports and Attributes
Table6-20 describes the ports that control OOB/beacon signaling.
Table 6-20:
TX OOB/Beacon Signaling Ports
Direction
Domain
Description
The decoding of RXSTATUS[2:0] depends on the setting of RX_STATUS_FMT:
?When RX_STATUS_FMT = PCIE:
RXSTATUS0[2:0]RXSTATUS1[2:0]
Out
RXUSRCLK2
RXSTATUS is not used for PCIe TXELECIDLE?When RX_STATUS_FMT = SATA:
RXSTATUS[0]: TXCOMSTART operation completeRXSTATUS[1]: COMWAKE signal received
RXSTATUS[2]: COMRESET/COMINIT signal received
TXCOMSTART0TXCOMSTART1TXCOMTYPE0TXCOMTYPE1TXELECIDLE0TXELECIDLE1
TXPOWERDOWN0[1:0]TXPOWERDOWN1[1:0]
In
TXUSRCLK2
Initiates the transmission of the COM* sequence selected by TXCOMTYPE (SATA only).
Selects the type of COM signal to send (SATA only):
In
TXUSRCLK2
0: COMRESET/COMINIT1: COMWAKE
In
TXUSRCLK2
When in the P2 power state, this signal controls whether an
electrical idle or a beacon indication is driven out onto the TX pair.Powers down the TX lanes. When in PCIe mode, the GTX_DUAL tile must be in the P2 power state (TXPOWERDOWN = 11) to generate beacon signaling. Use TXPOWERDOWN = 00 for SATA OOB signaling.
Port
InTXUSRCLK2
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
TX Out-of-Band/Beacon Signaling
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 6:GTX Transmitter (TX)
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC2S150-4FG256C中文规格书 - 图文
