MEMORY存储芯片DS1232LPSN-2+T&R中文规格书 - 图文

?? Super-low power version of DS1232?? 50 μA quiescent current

?? Halts and restarts an out-of-controlmicroprocessor

?? Automatically restarts microprocessor afterpower failure

?? Monitors pushbutton for external override?? Accurate 5% or 10% microprocessor powersupply monitoring

??8-pin DIP, 8-pin SOIC or space saving μ-SOPpackage available

??Optional 16-pin SOIC package available??Industrial temperature -40°C to +85°Cavailable, designated N

FEATURESPIN ASSIGNMENTPBRSTTDTOLGND12348765VCCSTRSTRSTNCPBRSTNCTDNCTOLDS1232LP 8-Pin DIP (300-mil)See Mech. Drawings SectionNCGND12345678161514131211109NCVCCNCSTNCRSTNCRSTDS1232LPS 16-Pin SOIC (300-mil)See Mech. Drawings SectionPBRSTTDTOLGND12348765VCCSTRSTRST12348765PBRSTTDTOLGNDVCCSTRSTRSTDS1232LPμ (118-mil μ-SOP)See Mech. Drawings SectionDS1232LPS-2 8-Pin SOIC (150-mil)See Mech. Drawings SectionPIN DESCRIPTION

PBRST

TD TOL GNDRST

RSTST

VCC

-Pushbutton Reset Input-Time Delay Set

-Selects 5% or 10% VCC Detect- Ground

-Reset Output (Active High)-Reset Output (Active Low, opendrain)

-Strobe Input-+5 Volt Power

DESCRIPTION

The DS1232LP/LPS Low Power MicroMonitor Chip monitors three vital conditions for amicroprocessor: power supply, software execution, and external over-ride. First, a precision temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-of-tolerancecondition occurs, an internal power-fail signal is generated which forces reset to the active state. WhenVCC returns to an in-tolerance condition, the reset signals are kept in the active state for a minimum of250 ms to allow the power supply and processor to stabilize.

111899

DS1232LP/LPS

The second function the DS1232LP/LPS performs is pushbutton reset control. The DS1232LP/LPS debounces the pushbutton input and guarantees an active reset pulse width of 250 ms minimum. The third function is a watchdog timer. The DS1232LP/LPS has an internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to timeout. The watchdog timer function can be set to operate on timeout settings of approximately 150 ms, 600 ms, and 1.2 seconds.

OPERATION - POWER MONITOR

The DS1232LP/LPS detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. When VCC falls below a preset level as defined by TOL, the VCCcomparator outputs the signals RST and RST . When TOL is connected to ground, the RST and RSTsignals become active as VCC falls below 4.75 volts. When TOL is connected to VCC, the RST and RSTsignals become active as VCC falls below 4.5 volts. The RST and RST are excellent control signals for a microprocessor, as processing is stopped at the last possible moments of valid VCC. On power-up, RSTand RST are kept active for a minimum of 250 ms to allow the power supply and processor to stabilize.

OPERATION - PUSHBUTTON RESET

The DS1232LP/LPS provides an input pin for direct connection to a pushbutton (Figure 1). The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed suchthat RST and RST signals of at least 250 ms minimum are generated. The 250 ms delay starts as the pushbutton reset input is released from low level.

OPERATION - WATCHDOG TIMER

The watchdog timer function forces RST and RST signals to the active state when the ST input is not stimulated for a predetermined time period. The time period is set by the TD input to be typically 150 ms with TD connected to ground, 600 ms with TD left unconnected, and 1.2 seconds with TD connected toVCC. The watchdog timer starts timing out from the set time period as soon as RST and RST are inactive.If a high-to-low transition occurs on the ST input pin prior to timeout, the watchdog timer is reset andbegins to timeout again. If the watchdog timer is allowed to timeout, then the RST and RST signals aredriven to the active state for 250 ms minimum. The ST input can be derived from microprocessor address signals, data signals, and/or control signals. When the microprocessor is functioning normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to timeout. To guarantee that the watchdog timer does not timeout, a high-to-low transition must occur at or less than the minimum shown in Table 1. A typical circuit example is shown in Figure 2.

DS1232LP/LPS

MICROMONITOR BLOCK DIAGRAM

DS1232LP/LPS

TIMING DIAGRAM: PUSHBUTTON RESET Figure 3

TIMING DIAGRAM: STROBE INPUT Figure 4

WATCHDOG TIME-OUTS Table 1

TIME-OUT

TDGNDFloatVCC

MIN62.5 ms250 ms500 ms

TYP150 ms600 ms1200 ms

MAX250 ms1000 ms2000 ms

DS1232LP/LPS

TIMING DIAGRAM: POWER-DOWN Figure 5

TIMING DIAGRAM: POWER-UP Figure 6