Power Control
when PLLPOWERDOWN is asserted, only the shared PMA PLL and all clocks derived from it are stopped.
Recovery from this power state is indicated by the assertion of the PLLLKDET signal on the tile whose REFCLKPWRDNB signal is asserted.
TX and RX Power Down
When the TX and RX power-down signals are used in non PCI Express implementations, TXPOWERDOWN and RXPOWERDOWN can be used independently. However, when these interfaces are used in non PCI Express applications, only two power states are supported, as shown in Table5-13. When using this power-down mechanism, the following must be True:????
TXPOWERDOWN[1] and TXPOWERDOWN[0] are connected together.RXPOWERDOWN[1] and RXPOWERDOWN[0] are connected together.TXDETECTRX must be strapped Low.
TXELECIDLE must be strapped to TXPOWERDOWN[1] and TXPOWERDOWN[0].
TX and RX Power States for Non PCI Express Operation
Description
P0 mode. Transceiver TX or RX is active sending or receiving data.P2 mode. Transceiver TX or RX is idle.
Table 5-13:
TXPOWERDOWN[1:0] or RXPOWERDOWN[1:0]
0011
Power Control Features for PCI Express Operation
The GTX_DUAL tile implements all of the functions needed for power control states compatible with those defined in the PCI Express and PIPE specifications. When
implementing PCI Express compatible power control, the following conditions must be met:??
Table 5-14:
The TXPOWERDOWN and RXPOWERDOWN signals on each GTX transceiver mustbe connected together to ensure that they are in the same state at all times.The REFCLKPWRDNB and PLLPOWERDOWN signals must be held in inactivestates.
TX and RX Power States for PCI Express Operation
TXELECIDLE
Description
The PHY is transmitting data. The MAC provides data bytes to be sent every clock cycle.
The PHY is not transmitting and is in the electrical idle state.
The PHY goes into loopback mode.Not permitted.
TXPOWERDOWN[1:0]
and TXDETECTRX
RXPOWERDOWN[1:0]
0
00 (P0 state)
011
0101
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 5:Tile Features
Table 5-14:TX and RX Power States for PCI Express Operation (Cont’d)
TXELECIDLE
Description
The MAC must always put the PHY into the electrical idle state while in P0s state. The PHY behavior is undefined if TXELECIDLE is deasserted while in P0s or P1.The PHY is not transmitting and is in the electrical idle state.
Not permitted. The MAC must always put the PHY into the electrical idle state while in P1. The PHY behavior is
undefined if TXELECIDLE is deasserted while in P0s or P1.The PHY is idle.
The PHY does a receiver detection operation.The PHY transmits beacon signalingThe PHY is idle.
TXPOWERDOWN[1:0]
and TXDETECTRX
RXPOWERDOWN[1:0]
0
01 (P0s state)
Don’t Care
1
Don’t Care
10 (P1 state)
01
11 (P2 state)
Don’t Care
01101
The GTX_DUAL acknowledges changes in the PCI Express power mode by asserting the PHYSTATUS signals for one clock cycle independently for each transceiver.
Power-Down Transition Times
The delays between changes in the power-down state when TXPOWERDOWN and RXPOWERDOWN are changed are controlled by the TRANS_TIME_FROM_P2,
TRANS_TIME_NON_P2, and TRANS_TIME_TO_P2 attributes as described in Table5-11.Each TRANS_TIME delay is set in terms of internal 25MHz clock cycles. The internal 25MHz clock rate is set using the CLK25_DIVIDER attribute and the reference clock rate. Equation5-6 is used to determine the actual rate.
CLK25_DIVIDER
Transition time [ns]=?----------------------------------------------?×TRANS_TIME attribute
??CLKIN
Equation5-6
Examples
The example in Figure5-10 shows the recommended method to power down an unused
tile or an unused transceiver in a tile. In the example, an uninstantiated GTX_DUAL tile has a 1 assigned to all power control ports to allow forwarding of a reference clock from GTX_DUAL neighbor tiles.
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Power Control
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 5:Tile Features
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 6:GTX Transmitter (TX)
Connecting TXUSRCLK and TXUSRCLK2
The FPGA TX interface includes two parallel clocks: TXUSRCLK and TXUSRCLK2.
TXUSRCLK is the internal clock for the PCS logic in the GTX transmitter. The required rate for TXUSRCLK depends on the internal datapath width of the GTX_DUAL tile
(INTDATAWIDTH), and the TX line rate of the GTX transmitter (“Parallel In to Serial Out,” page 149 describes how the TX line rate is determined). Equation6-1 shows how to calculate the required rate for TXUSRCLK.
Line Rate
TXUSRCLK Rate=----------------------------------------------------------------Internal Datapath Width
Equation6-1
TXUSRCLK2 is the main synchronization clock for all signals into the TX side of the GTX transceiver. Most signals into the TX side of the GTX transceiver are sampled on the
positive edge of TXUSRCLK2. TXUSRCLK2 and TXUSRCLK have a fixed-rate relationship based on the TXDATAWIDTH setting. Equation6-2 through Equation6-4 show how to calculate the required rate for TXUSRCLK2 based on TXUSRCLK for TXDATAWIDTH={0,1,2}.
TXDATAWIDTH=0: FTXUSRCLK2=2xFTXUSRCLKTXDATAWIDTH=1: FTXUSRCLK2=FTXUSRCLKTXDATAWIDTH=2: FTXUSRCLK2=FTXUSRCLK/2
Equation6-2Equation6-3Equation6-4
The following rules about the relationships between clocks must be observed for TXUSRCLK, TXUSRCLK2, and CLKIN:?
TXUSRCLK and TXUSRCLK2 must be positive-edge aligned, with as little skew aspossible between them. As a result, low-skew clock resources (BUFGs and BUFRs)should be used to drive TXUSRCLK and TXUSRCLK2. When TXUSRCLK and
TXUSRCLK2 have the same frequency, the same clock resource is used to drive both.When the two clocks have different frequencies, TXUSRCLK is used to deriveTXUSRCLK2 through the multiplication or division of TXUSRCLK. The designermust ensure that the two are positive-edge aligned. The “Examples” section showsvarious clock configurations that meet this requirement.
Even though they might run at different frequencies, TXUSRCLK, TXUSRCLK2, andCLKIN must have the same oscillator as their source. Thus TXUSRCLK and
TXUSRCLK2 must be multiplied or divided versions of CLKIN. The GTX transceiverprovides access to CLKIN in two ways: the REFCLKOUT pin (shared by both GTXtransceivers in the GTX_DUAL tile) and the TXOUTCLK pin. The “Examples” sectionshows several clock configurations with each pin.
REFCLKOUT is the same as CLKIN. It is free-running and operates even before theshared PMA PLL is locked. However, because REFCLKOUT uses the CLKIN rate, itcan require multiplication and division to produce the required rates for TXUSRCLKand TXUSRCLK2.
TXOUTCLK provides a copy of CLKIN already divided to the TXUSRCLK rate,potentially requiring fewer dividers. However, TXOUTCLK is not free-running. It isonly valid after the shared PMA PLL is locked and cannot be used when TX phasealignment is turned on (see “TX Buffering, Phase Alignment, and TX SkewReduction,” page 141).
?
?
?
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC2S150-6CS144C中文规格书 - 图文
