FPGA可编程逻辑器件芯片XQR1701LCC44V中文规格书 - 图文

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Differential Pair Labeling

A pin supports differential standards if the pin is labeled in the format “Lxxy_#”. The pin name suffix has the following significance. Figure40 provides a specific example showing a differential input to and a differential output from Bank 2.????

‘L’ indicates differential capability.

‘y’ is replaced by ‘P’ for the true signal or ‘N’ for the inverted. These two pins form one differential pin-pair.‘#’ is an integer, 0 through 7, indicating the associated I/O bank.

If unused, these pins are in a high impedance state. The Bitstream generator option UnusedPin enables a pull-up or pull-down resistor on all unused I/O pins.

Behavior from Power-On through End of Configuration

During the configuration process, all pins that are not actively involved in the configuration process are in a high-impedance state. The CONFIG- and JTAG-type pins have an internal pull-up resistor to VCCAUX during configuration. For all other I/O pins, the HSWAP_EN input determines whether or not pull-up resistors are activated during configuration. HSWAP_EN=0 enables the pull-up resistors. HSWAP_EN=1 disables the pull-up resistors allowing the pins to float, which is the desired state for hot-swap applications.

X-Ref Target - Figure 40Bank 0Bank 7Bank 1Bank 3Bank 2Pair NumberIO_L38P_2IO_L38N_2IO_L39P_2IO_L39N_2Bank NumberPositive Polarity,True ReceiverBank 6Bank 5Bank 4Figure 40:Differential Pair Labelling

Negative Polarity,Inverted ReceiverDS099-4_01_091710DUAL Type: Dual-Purpose Configuration and I/O Pins

These pins serve dual purposes. The user-I/O pins are temporarily borrowed during the configuration process to load

configuration data into the FPGA. After configuration, these pins are then usually available as a user I/O in the application. If a pin is not applicable to the specific configuration mode—controlled by the mode select pins M2, M1, and M0—then the pin behaves as an I/O-type pin.

There are 12 dual-purpose configuration pins on every package, six of which are part of I/O Bank 4, the other six part of I/O Bank 5. Only a few of the pins in Bank 4 are used in the Serial configuration modes.See Pin Behavior During Configuration, page122.

Serial Configuration Modes

This section describes the dual-purpose pins used during either Master or Slave Serial mode. See Table75 for Mode Select pin settings required for Serial modes. All such pins are in Bank 4 and powered by VCCO_4.

In both the Master and Slave Serial modes, DIN is the serial configuration data input. The D1-D7 inputs are unused in serial mode and behave like general-purpose I/O pins.

In all the cases, the configuration data is synchronized to the rising edge of the CCLK clock signal.

The DIN, DOUT, and INIT_B pins can be retained in the application to support reconfiguration by setting the Persist bitstream generation option. However, the serial modes do not support device readback.

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Pinout Descriptions

Table 71:Dual-Purpose Pins Used in Master or Slave Serial Mode

Pin NameDIN

DirectionInput

Description

Serial Data Input:

During the Master or Slave Serial configuration modes, DIN is the serial configuration data input, and all data is synchronized to the rising CCLK edge. After configuration, this pin is available as a user I/O. This signal is located in Bank 4 and its output voltage determined by VCCO_4.

The BitGen option Persist permits this pin to retain its configuration function in the User mode.Serial Data Output:

In a multi-FPGA design where all the FPGAs use serial mode, connect the DOUT output of one FPGA—in either Master or Slave Serial mode—to the DIN input of the next FPGA—in Slave Serial mode—so that configuration data passes from one to the next, in daisy-chain fashion. This “daisy chain” permits sequential configuration of multiple FPGAs.

This signal is located in Bank 4 and its output voltage determined by VCCO_4.

The BitGen option Persist permits this pin to retain its configuration function in the User mode.Initializing Configuration Memory/Configuration Error:

Just after power is applied, the FPGA produces a Low-to-High transition on this pin indicating that initialization (i.e., clearing) of the configuration memory has finished. Before entering the User mode, this pin functions as an open-drain output, which requires a pull-up resistor in order to produce a High logic level. In a multi-FPGA design, tie (wire AND) the INIT_B pins from all FPGAs together so that the common node transitions High only after all of the FPGAs have been successfully initialized.

Externally holding this pin Low beyond the initialization phase delays the start of configuration. This action stalls the FPGA at the configuration step just before the mode select pins are sampled.During configuration, the FPGA indicates the occurrence of a data (i.e., CRC) error by asserting INIT_B Low.

This signal is located in Bank 4 and its output voltage determined by VCCO_4.

The BitGen option Persist permits this pin to retain its configuration function in the User mode.

DOUTOutput

INIT_B

Bidirectional (open-drain)

X-Ref Target - Figure 41I/O Bank 4 (VCCO_4)I/O Bank 5 (VCCO_5)

D31

D41

Low NibbleD5D61

D70(LSB)

Configuration Data Byte

0xFC =

D01(MSB)

High Nibble

D1D21

Figure 41:Configuration Data Byte Mapping to D0-D7 Bits

Parallel Configuration Modes (SelectMAP)

This section describes the dual-purpose configuration pins used during the Master and Slave Parallel configuration modes,

sometimes also called the SelectMAP modes. In both Master and Slave Parallel configuration modes, D0-D7 form the byte-wide configuration data input. See Table75 for Mode Select pin settings required for Parallel modes.

As shown in Figure41, D0 is the most-significant bit while D7 is the least-significant bit. Bits D0-D3 form the high nibble of the byte and bits D4-D7 form the low nibble.

In the Parallel configuration modes, both the VCCO_4 and VCCO_5 voltage supplies are required and must both equal the voltage of the attached configuration device, typically either 2.5V or 3.3V.

Assert Low both the chip-select pin, CS_B, and the read/write control pin, RDWR_B, to write the configuration data byte presented on the D0-D7 pins to the FPGA on a rising-edge of the configuration clock, CCLK. The order of CS_B and RDWR_B does not matter, although RDWR_B must be asserted throughout the configuration process. If RDWR_B is de-asserted during configuration, the FPGA aborts the configuration operation.

After configuration, these pins are available as general-purpose user I/O. However, the SelectMAP configuration interface is optionally available for debugging and dynamic reconfiguration. To use these SelectMAP pins after configuration, set the Persist bitstream generation option.

The Readback debugging option, for example, requires the Persist bitstream generation option. During Readback mode, assert CS_B Low, along with RDWR_B High, to read a configuration data byte from the FPGA to the D0-D7 bus on a rising CCLK edge. During Readback mode, D0-D7 are output pins.

In all the cases, the configuration data and control signals are synchronized to the rising edge of the CCLK clock signal.

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Pinout Descriptions

PROG_B InputPower-upLow-going pulseAutomatically initiates configuration process.ResponseInitiate (re-)configuration process and continue to completion.Initiate (re-)configuration process and stall process at step where configuration memory is cleared. Process is stalled until PROG_B returns High.If the configuration process is started, continue to completion. If configuration process is complete, stay in User mode.Extended Low1DONE: Configuration Done, Delay Start-Up Sequence

The FPGA produces a Low-to-High transition on this pin indicating that the configuration process is complete. The bitstream generator option DriveDone determines whether this pin functions as a totem-pole output that can drive High or as an open-drain output. If configured as an open-drain output—which is the default behavior—then a pull-up resistor is required to produce a High logic level. There is a bitstream option that provides an internal pull-up resistor, otherwise an external pull-up resistor is required.

The open-drain option permits the DONE lines of multiple FPGAs to be tied together, so that the common node transitions High only after all of the FPGAs have completed configuration. Externally holding the open-drain DONE pin Low delays the start-up sequence, which marks the transition to user mode.

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Pinout Descriptions

Once the FPGA enters User mode after completing configuration, the DONE pin no longer drives the DONE pin Low. The bitstream generator option DonePin determines whether or not a pull-up resistor is present on the DONE pin to pull the pin to VCCAUX. If the pull-up resistor is eliminated, then the DONE pin must be pulled High using an external pull-up resistor or one of the FPGAs in the design must actively drive the DONE pin High via the DriveDone bitstream generator option.The bitstream generator option DriveDone causes the FPGA to actively drive the DONE output High after configuration. This option should only be used in single-FPGA designs or on the last FPGA in a multi-FPGA daisy-chain.

By default, the bitstream generator software retains the pull-up resistor and does not actively drive the DONE pin as highlighted in Table74, which shows the interaction of these bitstream options in single- and multi-FPGA designs.Table 74:DonePin and DriveDone Bitstream Option Interaction

DonePinPullnonePullnonePullnonePullnonePullupPullupPullupPullup

DriveDone

NoNoYesYesNoNoYesYes

Single- or Multi- FPGA Design

SingleMultiSingleMultiSingleMultiSingleMulti

Comments

External pull-up resistor, with value between 330Ω to 3.3kΩ, required on DONE.External pull-up resistor, with value between 330Ω to 3.3kΩ, required on common node connecting to all DONE pins.OK, no external requirements.

DriveDone on last device in daisy-chain only. No external requirements.

OK, but pull-up on DONE pin has slow rise time. May require 330Ω pull-up resistor for high CCLK frequencies.

External pull-up resistor, with value between 330Ω to 3.3kΩ, required on common node connecting to all DONE pins.OK, no external requirements.

DriveDone on last device in daisy-chain only. No external requirements.

M2, M1, M0: Configuration Mode Selection

The M2, M1, and M0 inputs select the FPGA configuration mode, as described in Table75. The logic levels applied to the mode pins are sampled on the rising edge of INIT_B.Table 75:Spartan-3 FPGA Mode Select Settings

Configuration ModeMaster SerialSlave SerialMaster ParallelSlave ParallelJTAGReservedReservedReserved

After ConfigurationNotes:

X=don’t care, either 0 or 1.

M201011001X

M101110010X

M001101100X

Before and during configuration, the mode pins have an internal pull-up resistor to VCCAUX, regardless of the HSWAP_EN pin. If the mode pins are unconnected, then the FPGA defaults to the Slave Serial configuration mode. After configuration successfully completes, any levels applied to these input are ignored. Furthermore, the bitstream generator options M0Pin, M1Pin, and M2Pin determines whether a pull-up resistor, pull-down resistor, or no resistor is present on its respective mode pin, M0, M1, or M2.

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: Pinout Descriptions

All VCCAUX inputs must be connected together and to the +2.5V voltage supply. Furthermore, there must be sufficient supply decoupling to guarantee problem-free operation, as described in XAPP623.

Because VCCAUX connects to the DCMs and the DCMs are sensitive to voltage changes, be sure that the VCCAUX supply and the ground return paths are designed for low noise and low voltage drop, especially that caused by a large number of simultaneous switching I/Os.

GND Type: Ground

All GND pins must be connected and have a low resistance path back to the various VCCO, VCCINT, and VCCAUX supplies.

Pin Behavior During Configuration

Table79 shows how various pins behave during the FPGA configuration process. The actual behavior depends on the values applied to the M2, M1, and M0 mode select pins and the HSWAP_EN pin. The mode select pins determine which of the DUAL type pins are active during configuration. In JTAG configuration mode, none of the DUAL-type pins are used for configuration and all behave as user-I/O pins.

All DUAL-type pins not actively used during configuration and all I/O-type, DCI-type, VREF-type, GCLK-type pins are high impedance (floating, three-stated, Hi-Z) during the configuration process. These pins are indicated in Table79 as shaded table entries or cells. These pins have a pull-up resistor to their associated VCCO if the HSWAP_EN pin is Low. When HSWAP_EN is High, these pull-up resistors are disabled during configuration.

Some pins always have an active pull-up resistor during configuration, regardless of the value applied to the HSWAP_EN pin. After configuration, these pull-up resistors are controlled by Bitstream Options.???

All the dedicated CONFIG-type configuration pins (CCLK, PROG_B, DONE, M2, M1, M0, and HSWAP_EN) have apull-up resistor to VCCAUX.

All JTAG-type pins (TCK, TDI, TMS, TDO) have a pull-up resistor to VCCAUX.

The INIT_B DUAL-purpose pin has a pull-up resistor to VCCO_4 or VCCO_BOTTOM, depending on package style.

After configuration completes, some pins have optional behavior controlled by the configuration bitstream loaded into the part. For example, via the bitstream, all unused I/O pins can be collectively configured as input pins with either a pull-up resistor, a pull-down resistor, or be left in a high-impedance state.Table 79:Pin Behavior After Power-Up, During Configuration

Configuration Mode Settings

Pin Name

Serial Modes

Master <0:0:0>

I/O: General-purpose I/O pinsIOIO_Lxxy_#

UnusedPinUnusedPin

SelectMap Parallel ModesMaster <0:1:1>

Slave <1:1:0>

Slave <1:1:1>

JTAG Mode <1:0:1>

Bitstream Configuration

Option