GTX Transmitter (TX)
This chapter shows how to configure and use each of the functional blocks inside the GTX transmitter.
Transmitter Overview
Each GTX transceiver in the GTX_DUAL tile includes an independent transmitter, which consists of a PCS and a PMA. Figure6-1 shows the functional blocks of the transmitter. Parallel data flows from the FPGA into the FPGA TX interface, through the PCS and PMA, and then out the TX driver as high-speed serial data. Refer to AppendixE, “Low Latency Design,” for latency information on this block diagram.
X-Ref Target - Figure 6-19TXTX TXOOBDriver&PreempPCISharedPMAPLLDivider87PISO4PolarityControlPhaseAdjustFIFOLoopback from RX (same channel)128B/10BEncoder1035TXGearboxFPGATXInterface6TX-PMATX-PCSPRBSGeneratorTX PIPE ControlFrom Shared PMA PLLUG198_c6_01_042407Figure 6-1:GTX TX Block Diagram
The key elements within the GTX transmitter are:1.2.3.4.5.6.7.8.9.
“FPGA TX Interface,” page 120
“Configurable 8B/10B Encoder,” page 129
“TX Buffering, Phase Alignment, and TX Skew Reduction,” page 141“TX Polarity Control,” page 147“TX Gearbox,” page 134“TX PRBS Generator,” page 148“Parallel In to Serial Out,” page 149“Configurable TX Driver,” page 150
“Receive Detect Support for PCI Express Operation,” page 153
10.“TX Out-of-Band/Beacon Signaling,” page 157
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
FPGA TX Interface
Table 6-1:FPGA TX Interface Ports (Cont’d)Port
DirectionClock Domain
Description
TXCHARDISPVAL and TXCHARDISPMODE allow control of the 8B/10B outgoing data disparity when 8B/10B encoding is enabled.
When 8B/10B encoding is disabled, TXCHARDISPVAL is used to extend the data bus for 10- and 20-bit TX interfaces. See “FPGA TX Interface,” page 120.
In
TXUSRCLK2
TXCHARDISPVAL[3] corresponds to TXDATA[31:24]TXCHARDISPVAL[2] corresponds to TXDATA[23:16]TXCHARDISPVAL[1] corresponds to TXDATA[15:8]TXCHARDISPVAL[0] corresponds to TXDATA[7:0]Table6-5, page133 shows how to use TXCHARDISPVAL to control the disparity of outgoing data when 8B/10B encoding is enabled.
The bus for transmitting data. The width of this port depends on TXDATAWIDTH:
TXCHARDISPVAL0[3:0]TXCHARDISPVAL1[3:0]
TXDATA0[31:0]TXDATA1[31:0]
InTXUSRCLK2
?TXDATAWIDTH = 0: TXDATA[7:0] = 8 bits wide?TXDATAWIDTH = 1: TXDATA[15:0] = 16 bits wide?TXDATAWIDTH = 2: TXDATA[31:0] = 32 bits wideWhen a 10-bit, 20-bit, or 40-bit bus is required, the
TXCHARDISPVAL and TXCHARDISPMODE ports from the 8B/10B encoder are concatenated with the TXDATA port. See Figure6-3, page123.
Selects the width of the TXDATA port.????
0: TXDATA is 8 bits or 10 bits wide1: TXDATA is 16 bits or 20 bits wide2: TXDATA is 32 bits or 40 bits wide3: Reserved
TXDATAWIDTH0[1:0]TXDATAWIDTH1[1:0]
InTXUSRCLK2
TXENC8B10BUSE0TXENC8B10BUSE1
TXENC8B10BUSE is set High to enable the 8B/10B encoder. INTDATAWIDTH must also be High.
In
TXUSRCLK2
0: 8B/10B encoder bypassed. This option reduces latency.1: 8B/10B encoder enabled. INTDATAWIDTH must be High.
This port provides a parallel clock generated by the GTX transceiver. This clock can be used to drive TXUSRCLK for one or more GTX transceivers. The rate of the clock depends on INTDATAWIDTH:
TXOUTCLK0TXOUTCLK1
OutN/A
?INTDATAWIDTH is Low: FTXOUTCLK = Line Rate/16?INTDATAWIDTH is High: FTXOUTCLK = Line Rate/20
Note:
?When INTDATAWIDTH is High, the duty cycle is 60/40instead of 50/50.
?When oversampling is enabled, the line rate in the
calculation of FTXOUTCLK is equal to the oversampled line rate, not the PMA line rate.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
FPGA TX Interface
Examples
Figure6-5 through Figure6-9 show different ways FPGA clock resources can be used to drive the parallel clocks for the TX interface.
TXOUTCLK Driving a GTX TX in 2-Byte Mode
In Figure6-5, TXOUTCLK is used to drive TXUSRCLK and TXUSRCLK2 for 2-byte mode (TXDATAWIDTH = 1).
X-Ref Target - Figure 6-5GTXTransceiverTXOUTCLKTXDATA16 or 20 BitsTXUSRCLKTXUSRCLK2BUFG orBUFR(1)UG198_c6_05_050707Notes:
1.Refer to the Virtex?-5 FPGA Data Sheet and the Virtex-5 FPGAConfiguration Guide for the maximum clock frequency and jitterlimitations of BUFR.
Figure 6-5:TXOUTCLK Drives TXUSRCLK and TXUSRCLK2 (2-Byte Mode)
TXOUTCLK Driving GTX TX in 4-Byte Mode
The example in Figure6-6 uses 4-byte wide datapaths (TXDATAWIDTH=2). TXOUTCLK drives TXUSRCLK, and TXOUTCLK is divided by two using a DCM or PLL to drive TXUSRCLK2.
X-Ref Target - Figure 6-6DCMCLKFBPLLLKDETTXOUTCLKBUFGTXUSRCLK2TXUSRCLKRSTCLKINLOCKEDCLK0CLKDVGTXTransceiverDesign InFPGATXDATA (32 or 40 bits)UG198_c6_06_051507Figure 6-6:DCM Provides Clocks for 4-Byte Wide Datapath
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 6:GTX Transmitter (TX)
Description
Enabling 8B/10B Encoding
To disable the 8B/10B encoder on a given GTX transceiver, TXENC8B10BUSE must be driven Low. To enable the 8B/10B encoder, TXENC8B10BUSE must be driven High. When the encoder is turned off, the operation of the TXDATA port is as described in “FPGA TX Interface.”
8B/10B Bit and Byte Ordering
The order of the bits after the 8B/10B encoder is the opposite of the order shown in AppendixC, “8B/10B Valid Characters,” because 8B/10B encoding requires bit a0 to be transmitted first, and the GTX transceiver always transmits the right-most bit first. To match with 8B/10B, the 8B/10B encoder in the GTX transceiver automatically reverses the bit order (Figure6-10).
For the same reason, when a 2-byte interface is used, the first byte to be transmitted (byte 0)must be placed on TXDATA[7:0], and the second placed on TXDATA[15:8]. When a4-byte interface is used, byte 0 must be placed on TXDATA[7:0], byte 1 must be placed onTXDATA[15:8], byte 2 must be placed on TXDATA[23:16], and byte 3 must be placed onTXDATA[31:24]. This placement ensures that the byte 0 bits are all sent before the byte 1bits, as required by 8B/10B encoding.
X-Ref Target - Figure 6-10TXDATAWIDTH = 11514131211109876543210TXDATAWIDTH = 076543210TXDATAH1G1F1E1D1C1B1A1H0G0F0E0D0C0B0A0TXDATAH0G0F0E0D0C0B0A08B/10B8B/10Bj1h1g1f1i1e1d1c1b1a1j0h0g0f0i0e0d0c0b0a0j0h0g0f0i0e0d0c0b0a0TransmittedLastTransmittedTransmittedFirstLastTXDATAWIDTH = 2TransmittedFirst313029282726252423222120191817161514131211109876543210TXDATAH3G3F3E3D3C3B3A3H2G2F2E2D2C2B2A2H1G1F1E1D1C1B1A1H0G0F0E0D0C0B0A08B/10Bj3h3g3f3i3e3d3c3b3a3j2h2g2f2i2e2d2c2b2a2j1h1g1f1i1e1d1c1b1a1j0h0g0f0i0e0d0c0b0a0TransmittedLastTransmittedFirstUG198_c6_10_090607Figure 6-10:8B/10B Encoding
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Configurable 8B/10B Encoder
TXCHARDISPMODE
0011
TXCHARDISPVAL
0101
Outgoing Disparity
Calculated normally by the 8B/10B encoderInverts normal running disparity when encoding TXDATA
Forces running disparity negative when encoding TXDATA
Forces running disparity positive when encoding TXDATA
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC6VSX315T-2FFG1759C中文规格书 - 图文
