Extended Temperature Usage
Micron’s DDR3 SDRAM support the optional extended case temperature (TC) range of0°C to 95°C. Thus, the SRT and ASR options must be used at a minimum.
The extended temperature range DRAM must be refreshed manually at 2x (double re-fresh) anytime the case temperature is above 85°C (and does not exceed 95°C). The
manual refresh requirement is accomplished by reducing the refresh period from 64msto 32ms. However, self refresh mode requires either ASR or SRT to support the extendedtemperature. Thus, either ASR or SRT must be enabled when TC is above 85°C or selfrefresh cannot be used until TC is at or below 85°C. Table 76 summarizes the two exten-ded temperature options and Table 77 summarizes how the two extended temperatureoptions relate to one another.
Table 76: Self Refresh Temperature and Auto Self Refresh Description
FieldSRTMR2 Bits7DescriptionIf ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate TOPER during self refresh:*MR2[7] = 0: Normal operating temperature range (0°C to 85°C)*MR2[7] = 1: Extended operating temperature range (0°C to 95°C)If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range issupported*MR2[7] = 0: SRT is disabledWhen ASR is enabled, the DRAM automatically provides SELF REFRESH power management func-tions, (refresh rate for all supported operating temperature values)*MR2[6] = 1: ASR is enabled (M7 must = 0)When ASR is not enabled, the SRT bit must be programmed to indicate TOPER during SELF REFRESHoperation*MR2[6] = 0: ASR is disabled; must use manual self refresh temperature (SRT)Self Refresh Temperature (SRT)Auto Self Refresh (ASR)ASR6Table 77: Self Refresh Mode Summary
MR2[6]MR2[7](ASR)(SRT)SELF REFRESH Operation0001Self refresh mode is supported in the normal temperaturerangePermitted Operating TemperatureRange for Self Refresh ModeNormal (0°C to 85°C)Self refresh mode is supported in normal and extended temper-Normal and extended (0°C to 95°C)ature ranges; When SRT is enabled, it increases self refreshpower consumptionSelf refresh mode is supported in normal and extended temper-Normal and extended (0°C to 95°C)ature ranges; Self refresh power consumption may be tempera-ture-dependentIllegal10111Gb: x4, x8, x16 DDR3L SDRAM
PRECHARGE Operation
PRECHARGE Operation
Input A10 determines whether one bank or all banks are to be precharged and, in thecase where only one bank is to be precharged, inputs BA[2:0] select the bank.
When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After abank is precharged, it is in the idle state and must be activated prior to any READ orWRITE commands being issued.
SELF REFRESH Operation
The SELF REFRESH operation is initiated like a REFRESH command except CKE is LOW.The DLL is automatically disabled upon entering SELF REFRESH and is automaticallyenabled and reset upon exiting SELF REFRESH.
All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid lev-els upon entry/exit and during self refresh mode operation. VREFDQ may float or notdrive VDDQ/2 while in self refresh mode under certain conditions:????
VSS < VREFDQ < VDD is maintained.
VREFDQ is valid and stable prior to CKE going back HIGH.
The first WRITE operation may not occur earlier than 512 clocks after VREFDQ is valid.All other self refresh mode exit timing requirements are met.
The DRAM must be idle with all banks in the precharge state (tRP is satisfied and nobursts are in progress) before a self refresh entry command can be issued. ODT mustalso be turned off before self refresh entry by registering the ODT ball LOW prior to theself refresh entry command (see On-Die Termination (ODT) ( for timing requirements).If RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.”After the self refresh entry command is registered, CKE must be held LOW to keep theDRAM in self refresh mode.
After the DRAM has entered self refresh mode, all external control signals, except CKEand RESET#, are “Don’t Care.” The DRAM initiates a minimum of one REFRESH com-mand internally within the tCKE period when it enters self refresh mode.
The requirements for entering and exiting self refresh mode depend on the state of theclock during self refresh mode. First and foremost, the clock must be stable (meetingtCK specifications) when self refresh mode is entered. If the clock remains stable andthe frequency is not altered while in self refresh mode, then the DRAM is allowed to exitself refresh mode after tCKESR is satisfied (CKE is allowed to transition HIGH tCKESRlater than when CKE was registered LOW). Since the clock remains stable in self refreshmode (no frequency change), tCKSRE and tCKSRX are not required. However, if theclock is altered during self refresh mode (if it is turned-off or its frequency changes),then tCKSRE and tCKSRX must be satisfied. When entering self refresh mode, tCKSREmust be satisfied prior to altering the clock's frequency. Prior to exiting self refreshmode, tCKSRX must be satisfied prior to registering CKE HIGH.
When CKE is HIGH during self refresh exit, NOP or DES must be issued for tXS time. tXSis required for the completion of any internal refresh already in progress and must besatisfied before a valid command not requiring a locked DLL can be issued to the de-vice. tXS is also the earliest time self refresh re-entry may occur. Before a command re-quiring a locked DLL can be applied, a ZQCL command must be issued, tZQOPER tim-ing must be met, and tXSDLL must be satisfied. ODT must be off during tXSDLL.
MEMORY存储芯片MT46V128M4P-5B J中文规格书
