找Memory、FPGA、二三极管、连接器、模块、光耦、电容电阻、单片机、处理器、晶振、传感器、 滤波器，
上深圳市美光存储技术有限公司
FeatureDescriptionVariable-precisionDSP?Native support for up to four signal processing precisionlevels:?Three 9 x 9, two 18 x 18, or one 27 x 27 multiplier in thesame variable-precision DSP block?One 36 x 36 multiplier using two variable-precision DSPblocks ( Arria V GZ devices only)?64-bit accumulator and cascade for systolic finite impulseresponses (FIRs)?Embedded internal coefficient memory?Preadder/subtractor for improved efficiencyMemory controller( Arria V GX, GT,SX, and ST only)Embeddedtransceiver I/ODDR3 and DDR2Embedded Hard IPblocks?Custom implementation:?Arria V GX and SX devices—up to 6.5536 Gbps?Arria V GT and ST devices—up to 10.3125 Gbps?Arria V GZ devices—up to 12.5 GbpsPCI Express? (PCIe?) Gen2 (x1, x2, or x4) and Gen1 (x1, x2,x4, or x8) hard IP with multifunction support, endpoint, androot portPCIe Gen3 (x1, x2, x4, or x8) support ( Arria V GZ only)Gbps Ethernet (GbE) and XAUI physical coding sublayer(PCS)Common Public Radio Interface (CPRI) PCSGigabit-capable passive optical network (GPON) PCS10-Gbps Ethernet (10GbE) PCS ( Arria V GZ only)Serial RapidIO? (SRIO) PCSInterlaken PCS ( Arria V GZ only)????????Clock networks?Up to 650 MHz global clock network?Global, quadrant, and peripheral clock networks?Clock networks that are not used can be powered down to reduce dynamic powerArria V Device OverviewSend Feedback
Package Plan
AV-510012020.06.15
Arria V Device OverviewSend FeedbackAV-510012020.06.15
Available Options
Arria V Device OverviewSend Feedback
AV-510012020.06.15
PMA Features
Table 20: PMA Features of the Transceivers in Arria V Devices
FeaturesCapabilityBackplane support?Arria V GX, GT, SX, and ST devices—Driving capability at6.5536 Gbps with up to 25 dB channel loss?Arria V GZ devices—Driving capability at 12.5 Gbps with up to16 dB channel loss?Arria V GX, GT, SX, and ST devices—Up to 10.3125 Gbps?Arria V GZ devices—Up to 12.5 GbpsChip-to-chip supportArria V Device OverviewSend Feedback
SoC with HPS
AV-510012020.06.15
SoC with HPS
Each SoC combines an FPGA fabric and an HPS in a single device. This combination delivers theflexibility of programmable logic with the power and cost savings of hard IP in these ways:
?Reduces board space, system power, and bill of materials cost by eliminating a discrete embeddedprocessor
?Allows you to differentiate the end product in both hardware and software, and to support virtually anyinterface standard
?Extends the product life and revenue through in-field hardware and software updates
HPS Features
The HPS consists of a dual-core Arm* Cortex-A9 MPCore* processor, a rich set of peripherals, and ashared multiport SDRAM memory controller, as shown in the following figure.
Figure 12: HPS with Dual-Core Arm Cortex-A9 MPCore Processor
ConfigurationControllerFPGA-to-HPSFPGAManagerDebugAccess PortETR(Trace)SD/MMC ControllerEthernetMAC (2x)USBOTG (2x)NAND Flash ControllerDMAControllerSTMLightweightHPS-to-FPGAHPS-to-FPGAFPGA FabricHPSMPU SubsystemFPGA-to-HPS SDRAMLevel 3InterconnectARM Cortex-A9 MPCoreCPU0CPU1ARM Cortex-A9ARM Cortex-A9with NEON/FPU,with NEON/FPU,32 KB Instruction Cache,32 KB Instruction Cache,32 KB Data Cache, and32 KB Data Cache, andMemory Management Memory Management UnitUnitACPSCULevel 2 Cache (512 KB)MultiportDDR SDRAMControllerwithOptional ECC64 KBBoot ROM64 KBOn-Chip RAMPeripherals(UART, Timer, IC, Watchdog Timer, GPIO, SPI, Clock Manager, Reset Manager, Scan Manager, System Manager, and Quad SPI Flash Controller)2Arria V Device OverviewSend Feedback
FPGA可编程逻辑器件芯片5AGXBA7D4F31I5N中文规格书
