NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8.29.8Power domains
The LPC17xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers.On the LPC17xx, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the
VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals.
Depending on the LPC17xx application, a design can use two power options to manage power consumption.
The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active.
LPC1769_68_67_66_65_64_63All information provided in this document is subject to legal disclaimers.? NXP Semiconductors N.V. 2020. All rights reserved.
power to operate,
Product data sheetRev. 9.10 — 8 September 2020 41 of 93
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
LPC17xxVDD(3V3)VSSVDD(REG)(3V3)REGULATORto I/O padsto coreto memories,peripherals, oscillators,PLLsMAIN POWER DOMAINVBATPOWERSELECTORULTRA LOW-POWERREGULATORBACKUP REGISTERSRTCX1RTCX232 kHzOSCILLATORRTC POWER DOMAINREAL-TIME CLOCKDACVDDAVREFPVREFNVSSAADC POWER DOMAINADC002aad978Fig 7.Power distribution8.30System control
8.30.1Reset
Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see description in Section 8.29.5). The wake-up timer ensures that reset remains asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. Once reset is
de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD threshold, the RSTOUT pin goes HIGH.
When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.
LPC1769_68_67_66_65_64_63All information provided in this document is subject to legal disclaimers.? NXP Semiconductors N.V. 2020. All rights reserved.
Product data sheetRev. 9.10 — 8 September 2020 42 of 93
MEMORY存储芯片MPC8308CVMADD中文规格书 - 图文
