Error Detection Block
You can enable the StratixIII device error detection block in the QuartusII software (refer to“Software Support” on page15–11). This block contains the logic necessary to calculate the 16-bit CRC signature for the configuration CRAM bits in the device.The CRC circuit continues running even if an error occurs. When a soft error occurs, the device sets the CRC_ERROR pin high. Two types of CRC detection check the configuration bits:
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The CRAM error checking ability (16-bit CRC) during user mode, for use by theCRC_ERROR pin.
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For each frame of data, the pre-calculated 16-bit CRC enters the CRC circuitright at the end of the frame data and determines whether or not there is anerror.
If an error occurs, the search engine starts to find the location of the error.You can shift the error messages out through the JTAG instruction or coreinterface logic while the error detection block continues running.
The JTAG interface reads out the 16-bit CRC result for the first frame and alsoshifts the 16-bit CRC bits to the 16-bit CRC storage registers for test purposes.You can deliberately introduce single error, double errors, or double errorsadjacent to each other to configuration memory for testing and designverification.
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1
The “Error Detection Registers” section focuses on the first type, the 16-bit CRC only when the device is in user mode.
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The 16-bit CRC that is embedded in every configuration data frame.
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During configuration, after a frame of data is loaded into the StratixIII device,the pre-computed CRC is shifted into the CRC circuitry.
At the same time, the CRC value for the data frame shifted-in is calculated. Ifthe pre-computed CRC and calculated CRC values do not match, nSTATUS isset low. Every data frame has a 16-bit CRC; therefore, there are many 16-bitCRC values for the whole configuration bitstream. Every device has differentlengths of the configuration data frame.
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Error Detection Registers
There is one set of 16-bit registers in the error detection circuitry that stores the computed CRC signature. A non-zero value on the syndrome register causes the CRC_ERROR pin to be set high. Figure15–1 shows the block diagram of the error detection circuitry, syndrome registers, and error injection block.
Stratix III Device Handbook, Volume 1
Chapter 16:Programmable Power and Temperature-Sensing Diodes in StratixIII Devices
StratixIII External Power Supply Requirements
ff
For possible values of each power supply, refer to the DC and Switching Characteristics of StratixIII Devices chapter in volume 2 of the StratixIII Device Handbook.
For detailed guidelines about how to connect and isolate VCCL and VCC power supply pins, refer to the StratixIII Device Family Pin Connections Guidelines.
Table16–2.StratixIII Power Supply RequirementsPower Supply PinVCCLVCCVCCD_PLLVCCA_PLLVCCPTVCCPGMVCCPDVCCIOVCC_CLKINVCCBATVREFGNDNotes to Table16–2:
(1)You can minimize the number of external power sources by driving the left column and supplies with the same voltage regulator. Note that
separate power planes, decoupling capacitors, and ferrite beads are required for VCCA_PLL and VCCPT when implementing this scheme.(2)VCCPD can be either 2.5 V, 3.0 V, or 3.3 V. For a 3.3-V standard, VCCPD = 3.3 V. For a 3.0-V I/O standard, VCCPD = 3.0V. For 2.5 V and below I/O
standards, VCCPD = 2.5V.
(3)This scheme is for VCCIO = 2.5V.
(4)There is one VREF pin per I/O bank. Use an external power supply or a resistor divider network to supply this voltage.
Recommended Board ConnectionVCCL VCCVCCD_PLLVCCA_PLL (1)VCCPGMVCCPD (2)VCCIO (3)VCCBATVREF (4)GNDI/O registers power supplyPLL digital power supplyPLL analog power supplyDescriptionSelectable core voltage power supplyPower supply for programmable power technologyConfiguration pins power supplyI/O pre-driver power supplyI/O power supplyDifferential clock input pins power supply (top and bottom I/O banks only)Battery back-up power supply for design security volatile key registerPower supply for voltage-referenced I/O standardsGroundStratix III Device Handbook, Volume 1
Chapter 16:Programmable Power and Temperature-Sensing Diodes in StratixIII DevicesTemperature Sensing Diode
Figure16–1 shows an example of power management for StratixIII devices.
Figure16–1.StratixIII Power Management Example (Note1), (2)
VINVoltage Regulator (Termination)Voltage Regulator (Core) Variable (1.1 V)Voltage Regulator (VCC) for the I/O Elements Fixed (1.1 V)VCCLTerminationResistorVCCStratix IIIUser I/OVoltage Regulator (VCCIO) I/O (2.5 V)Voltage Regulator (VCCPD) 2.5 V Voltage Regulator (VCCPGM/) Fixed (2.5 V)VCCIOVCCPDVCCPGMVCCPTVCCA_PLLVREFVoltage ReferenceVoltage Regulator (VCCPT)Fixed (2.5 V)Voltage Regulator (VCCA_PLL) Fixed (2.5 V)Notes to Figure16–1:
(1)When VCCL = 0.9V, you need a separate voltage regulator.
(2)When VCCL = 0.9V, VCCPT and VCC must be ramped before VCCL to minimize VCCL standby current during VCCPT and VCC ramping to full rail.
Temperature Sensing Diode
Knowing the junction temperature is crucial for thermal management. A StratixIII device monitors its die temperature with an embedded temperature sensing diode (TSD). This is done by sensing the voltage level across the TSD. Each temperature level produces a unique voltage across the diode. Use an external analog-to-digital converter that measures the voltage difference across the TSD and then converts it to a temperature reading.
Stratix III Device Handbook, Volume 1
Chapter 16:Programmable Power and Temperature-Sensing Diodes in StratixIII Devices
Conclusion
External Pin Connections
The StratixIII TSD, located in the top-right corner of the die, requires two pins for voltage reference. Connect the TEMPDIODEP and TEMPDIODEN pins to the external analog-to-digital converter, as shown in Figure16–2.
Figure16–2.TEMPDIODEP and TEMPDIODEN External Pin Connections
Temperature Sensing deviceTEMPDIODEPTSDStratixIIITEMPDIODENThe TSD is a very sensitive circuit which can be influenced by the noise coupled from traces on the board, and possibly within the device package itself, depending on device usage. The interfacing device registers temperature based on milivolts of difference as seen at the TSD. Switching I/O near the TSD pins can affect the temperature reading. Altera recommends you take temperature readings during periods of no activity in the device (for example, standby mode where no clocks are toggling in the device), such as when the nearby I/Os are at a DC state and the clock networks in the device are disabled.
Figure16–3.TSD Connections
Temperature-Sensing DeviceTEMPDIODEPTEMPDIODENStratix IIIConclusion
As process geometries get smaller, power and thermal management is becoming more crucial in FPGA designs. StratixIII devices offer programmable power technology and selectable core voltage options for low-power operation. Use these features, along with speed grade choices, in different permutations to get the best power and
performance combination. Taking advantage of the silicon, the QuartusII software is able to manipulate designs to use the best combination to achieve the lowest power at the required performance.
For thermal management, use the StratixIII temperature sensing diode with an
external analog-to-digital converter in production devices. This allows you to easily incorporate this feature in your designs. Being able to monitor the junction
temperature of the device at any time also allows you to control air flow to the device and save power for the whole system.
Stratix III Device Handbook, Volume 1
Chapter 16:Programmable Power and Temperature-Sensing Diodes in StratixIII DevicesChapter Revision History
Date and RevisionFebruary 2009,version 1.5October 2008,version 1.4May 2008,version 1.3Changes MadeRemoved “Referenced Documents” section.■Summary of Changes—Updated “Introduction”, “Temperature Sensing Diode”, “External PinConnections”, and “Conclusion” sections.Updated new Document Format.Updated Figure 16–1.Updated Table 16–2.Updated “External Pin Connections” section.Added material to note 3 of Table 16–2.Updated Figure 16–1 and Figure 16–3.Removed old version of Figure 16-2.Removed section “Architecture Description”.Removed material from the sections “Introduction”, “TemperatureSensing Diode”, “External Pin Connections”, and “Conclusion”.Added new section “Referenced Documents”.Added live links for references.—■■■■■■■—October 2007,version 1.2■■Minor update.■■May 2007, version 1.1November 2006,version 1.0Replaced all instances of VCCR with VCCPTInitial Release.Minor update.—Stratix III Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP1S30F1020C5N中文规格书 - 图文
